######################################################################
#
# MPLAB IDE .dev File Generated by `pic2dev.py'
#
# Device: PIC16F505
# Family: 16c5x
# Datasheet: 41236
# Programming Spec: 41226
# Date: Tue Apr 30 09:40:06 2013
#
######################################################################


######################################################################
#
# Memory Regions & Other General Device Information
#
######################################################################

vpp (range=10.000-12.000 dflt=11.000)
vdd (range=2.500-5.500 dfltrange=3.000-5.500 nominal=5.000)
pgming (memtech=ee tries=1 lvpthresh=0)
    wait (pgm=3000 eedata=2000 cfg=2000 userid=2000 erase=10000 lvpgm=2000)
    latches (pgm=1 eedata=1 cfg=1 userid=1)
EraseAlg=1
HWStackDepth=2
breakpoints (numhwbp=1 datacapture=false idbyte=x)
calmem (region=0x3ff-0x3ff)
testmem (region=0x400-0x43f)
userid (region=0x400-0x403)
cfgmem (region=0xfff-0xfff)
pgmmem (region=0x0-0x3ff)
NumBanks=4
MirrorRegs (0x0-0x7 0x20-0x27 0x40-0x47 0x60-0x67)
MirrorRegs (0x8-0xf 0x28-0x2f 0x48-0x4f 0x68-0x6f)

######################################################################
#
# Special Function Registers
#
######################################################################

sfr (key=INDF addr=0x0 size=1 flags=i access='u u u u u u u u')
    reset (por='--------' mclr='--------')
    bit (names='INDF' width='8')
sfr (key=TMR0 addr=0x1 size=1 access='rw rw rw rw rw rw rw rw')
    reset (por='xxxxxxxx' mclr='uuuuuuuu')
    bit (names='TMR0' width='8')
    stimulus (scl=rwb pcfiles=w regfiles=w type=int)
sfr (key=PCL addr=0x2 size=1 access='rw rw rw rw rw rw rw rw')
    reset (por='11111111' mclr='11111111')
    bit (names='PCL' width='8')
    stimulus (scl=rwb pcfiles=rw regfiles=w)
sfr (key=STATUS addr=0x3 size=1 access='rw r rw r r rw rw rw')
    reset (por='0-011xxx' mclr='q-0qquuu')
    bit (names='RBWUF - PA0 nTO nPD Z DC C' width='1 1 1 1 1 1 1 1')
sfr (key=FSR addr=0x4 size=1 access='r rw rw rw rw rw rw rw')
    reset (por='100xxxxx' mclr='100uuuuu')
    bit (names='FSR' width='8')
    stimulus (scl=rwb pcfiles=rw regfiles=w)
sfr (key=OSCCAL addr=0x5 size=1 access='rw rw rw rw rw rw rw u')
    reset (por='xxxxxxx-' mclr='uuuuuuu-')
    bit (names='CAL -' width='7 1')
sfr (key=PORTB addr=0x6 size=1 access='u u rw rw r rw rw rw')
    reset (por='--xxxxxx' mclr='--uuuuuu')
    bit (names='- - RB5 RB4 RB3 RB2 RB1 RB0' width='1 1 1 1 1 1 1 1')
    bit (tag=scl names='RB' width='8')
    stimulus (scl=rwb pcfiles=rw regfiles=rw)
sfr (key=PORTC addr=0x7 size=1 access='u u rw rw rw rw rw rw')
    reset (por='--xxxxxx' mclr='--uuuuuu')
    bit (names='- - RC5 RC4 RC3 RC2 RC1 RC0' width='1 1 1 1 1 1 1 1')
    bit (tag=scl names='RC' width='8')
    stimulus (scl=rwb pcfiles=rw regfiles=rw)

######################################################################
#
# Non Memory-Mapped Registers
#
# (Conditionally visible SFRs appear as NMMRs in the "Special Function
# Registers" section.)
#
######################################################################

HasNMMR=1
nmmr (key=WREG addr=0x0 size=1 access='rw rw rw rw rw rw rw rw')
    reset (por='qqqqqqqq' mclr='qqqqqqqq')
    bit (names='WREG' width='8')
nmmr (key=STKPTR addr=0x1 size=1 flags=h access='rw rw rw rw rw rw rw rw')
    reset (por='00000000' mclr='00000000')
    bit (names='STKPTR' width='8')
nmmr (key=TRISB addr=0x3 size=1 access='u u rw rw rw rw rw rw')
    reset (por='--111111' mclr='--111111')
    bit (names='- - TRISB5 TRISB4 TRISB3 TRISB2 TRISB1 TRISB0' width='1 1 1 1 1 1 1 1')
nmmr (key=TRISC addr=0x4 size=1 access='u u rw rw rw rw rw rw')
    reset (por='--111111' mclr='--111111')
    bit (names='- - TRISC5 TRISC4 TRISC3 TRISC2 TRISC1 TRISC0' width='1 1 1 1 1 1 1 1')
nmmr (key=OPTION_REG addr=0x5 size=1 access='rw rw rw rw rw rw rw rw')
    reset (por='11111111' mclr='11111111')
    bit (names='nGPWU nGPPU T0CS T0SE PSA PS' width='1 1 1 1 1 3')
NMMRObjSize=5

######################################################################
#
# Configuration Registers
#
######################################################################

cfgbits (key=CONFIG addr=0xfff unused=0x0)
    field (key=OSC mask=0x7 desc="Oscillator Selection bits")
        setting (req=0x7 value=0x7 desc="External RC oscillator/CLKOUT function on RB4/OSC2/CLKOUT pin")
        setting (req=0x7 value=0x6 desc="External RC oscillator/RB4 function on RB4/OSC2/CLKOUT pin")
        setting (req=0x7 value=0x5 desc="Internal RC oscillator/CLKOUT function on RB4/OSC2/CLKOUT pin")
        setting (req=0x7 value=0x4 desc="Internal RC oscillator/RB4 function on RB4/OSC2/CLKOUT pin")
        setting (req=0x7 value=0x3 desc="EC oscillator/RB4 function on RB4/OSC2/CLKOUT pin")
        setting (req=0x7 value=0x2 desc="HS oscillator")
        setting (req=0x7 value=0x1 desc="XT oscillator")
        setting (req=0x7 value=0x0 desc="LP oscillator")
    field (key=WDT mask=0x8 desc="Watchdog Timer Enable bit")
        setting (req=0x8 value=0x8 desc="Enabled")
        setting (req=0x8 value=0x0 desc="Disabled")
    field (key=CP mask=0x10 desc="Code Protection bit")
        setting (req=0x10 value=0x10 desc="Disabled")
            checksum (type=0x0 protregion=0x0-0x0)
        setting (req=0x10 value=0x0 desc="Enabled")
            checksum (type=0x20 protregion=0x40-0x3fe)
    field (key=MCLRE mask=0x20 desc="RB3/MCLR Pin Function Select bit")
        setting (req=0x20 value=0x20 desc="Enabled")
        setting (req=0x20 value=0x0 desc="Disabled")
