######################################################################
#
# MPLAB IDE .dev File Generated by `pic2dev.py'
#
# Device: PIC12F519
# Family: 16c5x
# Datasheet: 41319
# Programming Spec: 41316
# Date: Tue Apr 30 09:40:05 2013
#
######################################################################


######################################################################
#
# Memory Regions & Other General Device Information
#
######################################################################

vpp (range=10.000-12.000 dflt=11.000)
vdd (range=2.000-5.500 dfltrange=3.000-5.500 nominal=5.000)
pgming (memtech=ee tries=1 lvpthresh=0 csumadd=64)
    wait (pgm=3000 eedata=2000 cfg=2000 userid=2000 erase=10000 lvpgm=2000)
    latches (pgm=1 eedata=1 cfg=1 userid=1)
EraseAlg=3
HWStackDepth=2
NumHWBP=1
flashdata (region=0x400-0x43f)
calmem (region=0x3ff-0x3ff)
userid (region=0x440-0x443)
testmem (region=0x440-0x49f)
cfgmem (region=0xfff-0xfff)
pgmmem (region=0x0-0x3ff)
NumBanks=2
MirrorRegs (0x2-0x4 0x22-0x24)
MirrorRegs (0x0-0x0 0x20-0x20)
MirrorRegs (0x7-0xf 0x27-0x2f)

######################################################################
#
# Special Function Registers
#
######################################################################

sfr (key=INDF addr=0x0 size=1 flags=i access='u u u u u u u u')
    reset (por='--------' mclr='--------')
    bit (names='INDF' width='8')
sfr (key=TMR0 addr=0x1 size=1 access='rw rw rw rw rw rw rw rw')
    reset (por='xxxxxxxx' mclr='uuuuuuuu')
    bit (names='TMR0' width='8')
    stimulus (scl=rwb pcfiles=w regfiles=w type=int)
sfr (key=PCL addr=0x2 size=1 access='rw rw rw rw rw rw rw rw')
    reset (por='11111111' mclr='11111111')
    bit (names='PCL' width='8')
    stimulus (scl=rwb pcfiles=rw regfiles=w)
sfr (key=STATUS addr=0x3 size=1 access='rw u rw r r rw rw rw')
    reset (por='00011xxx' mclr='q-0qquuu')
    bit (names='RBWUF - PA0 nTO nPD Z DC C' width='1 1 1 1 1 1 1 1')
sfr (key=FSR addr=0x4 size=1 access='r r rw rw rw rw rw rw')
    reset (por='110xxxxx' mclr='110uuuuu')
    bit (names='FSR' width='8')
    stimulus (scl=rwb pcfiles=rw regfiles=w)
sfr (key=OSCCAL addr=0x5 size=1 access='rw rw rw rw rw rw rw u')
    reset (por='1111111-' mclr='1111111-')
    bit (names='CAL -' width='7 1')
sfr (key=GPIO addr=0x6 size=1 access='u u rw rw r rw rw rw')
    reset (por='--xxxxxx' mclr='--uuuuuu')
    bit (names='- - GP5 GP4 GP3 GP2 GP1 GP0' width='1 1 1 1 1 1 1 1')
    bit (tag=scl names='GP' width='8')
    stimulus (scl=rwb pcfiles=rw regfiles=rw)
sfr (key=EECON addr=0x21 size=1 access='u u u rw rw rw rs rs')
    reset (por='---00000' mclr='---00000')
    bit (names='- - - FREE WRERR WREN WR RD' width='1 1 1 1 1 1 1 1')
    stimulus (scl=rwb pcfiles=rw regfiles=w)
sfr (key=EEDATA addr=0x25 size=1 access='rw rw rw rw rw rw rw rw')
    reset (por='xxxxxxxx' mclr='uuuuuuuu')
    bit (names='EEDATA' width='8')
    stimulus (scl=rwb pcfiles=rw regfiles=rw)
sfr (key=EEADR addr=0x26 size=1 access='u u rw rw rw rw rw rw')
    reset (por='--xxxxxx' mclr='--uuuuuu')
    bit (names='EEADR' width='8')
    stimulus (scl=rwb pcfiles=rw regfiles=w)

######################################################################
#
# Non Memory-Mapped Registers
#
# (Conditionally visible SFRs appear as NMMRs in the "Special Function
# Registers" section.)
#
######################################################################

HasNMMR=1
nmmr (key=WREG addr=0x0 size=1 access='rw rw rw rw rw rw rw rw')
    reset (por='qqqqqqqq' mclr='qqqqqqqq')
    bit (names='WREG' width='8')
nmmr (key=STKPTR addr=0x1 size=1 flags=h access='rw rw rw rw rw rw rw rw')
    reset (por='00000000' mclr='00000000')
    bit (names='STKPTR' width='8')
nmmr (key=TRISGPIO addr=0x3 size=1 access='u u rw rw rw rw rw rw')
    reset (por='--111111' mclr='--111111')
    bit (names='- - TRISGPIO5 TRISGPIO4 TRISGPIO3 TRISGPIO2 TRISGPIO1 TRISGPIO0' width='1 1 1 1 1 1 1 1')
nmmr (key=OPTION_REG addr=0x5 size=1 access='rw rw rw rw rw rw rw rw')
    reset (por='11111111' mclr='11111111')
    bit (names='nRBWU nRBPU T0CS T0SE PSA PS' width='1 1 1 1 1 3')
NMMRObjSize=4

######################################################################
#
# Configuration Registers
#
######################################################################

cfgbits (key=CONFIG addr=0xfff unused=0x0)
    field (key=OSC mask=0x3 desc="Oscillator Selection bits")
        setting (req=0x3 value=0x0 desc="LP Osc With 18 ms DRT")
        setting (req=0x3 value=0x1 desc="XT Osc With 18 ms DRT")
        setting (req=0x3 value=0x2 desc="INTRC With 1 ms DRT")
        setting (req=0x3 value=0x3 desc="EXTRC With 1 ms DRT")
    field (key=WDTE mask=0x4 desc="Watchdog Timer Enable bit")
        setting (req=0x4 value=0x4 desc="Enabled")
        setting (req=0x4 value=0x0 desc="Disabled")
    field (key=CP mask=0x8 desc="Code Protection bit")
        setting (req=0x8 value=0x8 desc="Disabled")
            checksum (type=0x0 protregion=0x0-0x0)
        setting (req=0x8 value=0x0 desc="Enabled")
            checksum (type=0x30 protregion=0x40-0x3fe)
    field (key=MCLRE mask=0x10 desc="Master Clear Enable bit")
        setting (req=0x10 value=0x10 desc="Enabled")
        setting (req=0x10 value=0x0 desc="Disabled")
    field (key=IOSCFS mask=0x20 desc="Internal Oscillator Frequency Select bit")
        setting (req=0x20 value=0x20 desc="8 MHz INTOSC Speed")
        setting (req=0x20 value=0x0 desc="4 MHz INTOSC Speed")
    field (key=CPDF mask=0x40 desc="Code Protection bit - Flash Data Memory")
        setting (req=0x40 value=0x40 desc="Disabled")
        setting (req=0x40 value=0x0 desc="Enabled")
