######################################################################
#
# MPLAB IDE .dev File Generated by `pic2dev.py'
#
# Device: PIC18F2331
# Family: 18xxxx
# Datasheet: 39616
# Programming Spec: 30500
# Date: Tue Apr 30 09:42:28 2013
#
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#
# Memory Regions & Other General Device Information
#
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vpp (range=9.000-13.250 dflt=13.000)
vdd (range=2.125-5.500 dfltrange=4.250-5.500 nominal=5.000)
pgming (memtech=ee tries=1 lvpthresh=4.500 panelsize=0x2000)
    wait (pgm=1000 eedata=4000 cfg=5000 userid=5000 erase=10000 lvpgm=1000 lverase=1000)
    latches (pgm=8 eedata=2 cfg=2 userid=8 rowerase=64)
HWStackDepth=31
breakpoints (numhwbp=1 datacapture=false idbyte=p)
testmem (region=0x200000-0x2000bf)
userid (region=0x200000-0x200007)
cfgmem (region=0x300000-0x30000d)
devid (region=0x3ffffe-0x3fffff idmask=0xffe0 id=0x8e0)
    ver (id=0x8e0 desc="a0")
    ver (id=0x8e1 desc="a1")
eedata (region=0x0-0xff)
bkbgvectmem (region=0x200028-0x200037)
pgmmem (region=0x0-0x1fff)
NumBanks=16
UnusedBankMask=0x7ff8
AccessBankSplitOffset=0x60
UnusedRegs (0xf00-0xf5f)

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#
# Special Function Registers
#
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sfr (key=DFLTCON addr=0xf60 size=1 access='u rw rw rw rw rw rw rw')
    reset (por='-0000000' mclr='-0000000')
    bit (names='- FLT4EN FLT3EN FLT2EN FLT1EN FLTCK' width='1 1 1 1 1 3')
    stimulus (scl=rwb regfiles=w)
sfr (key=CAP3CON addr=0xf61 size=1 access='u rw rw u rw rw rw rw')
    reset (por='-10-0000' mclr='-10-0000')
    bit (names='- CAP3REN CAP3TMR - CAP3M' width='1 1 1 1 4')
    stimulus (scl=rwb regfiles=w)
sfr (key=CAP2CON addr=0xf62 size=1 access='u rw rw u rw rw rw rw')
    reset (por='-10-0000' mclr='-10-0000')
    bit (names='- CAP2REN CAP2TMR - CAP2M' width='1 1 1 1 4')
    stimulus (scl=rwb regfiles=w)
sfr (key=CAP1CON addr=0xf63 size=1 access='u rw rw u rw rw rw rw')
    reset (por='-10-0000' mclr='-10-0000')
    bit (names='- CAP1REN CAP1TMR - CAP1M' width='1 1 1 1 4')
    stimulus (scl=rwb regfiles=w)
sfr (key=CAP3BUFL addr=0xf64 size=1 access='rw rw rw rw rw rw rw rw')
    reset (por='xxxxxxxx' mclr='uuuuuuuu')
    bit (names='CAP3BUFL' width='8')
    stimulus (scl=rwb regfiles=w)
sfr (key=CAP3BUFH addr=0xf65 size=1 access='rw rw rw rw rw rw rw rw')
    reset (por='xxxxxxxx' mclr='uuuuuuuu')
    bit (names='CAP3BUFH' width='8')
    stimulus (scl=rwb regfiles=w)
sfr (key=CAP2BUFL addr=0xf66 size=1 access='rw rw rw rw rw rw rw rw')
    reset (por='xxxxxxxx' mclr='uuuuuuuu')
    bit (names='CAP2BUFL' width='8')
    stimulus (scl=rwb)
sfr (key=CAP2BUFH addr=0xf67 size=1 access='rw rw rw rw rw rw rw rw')
    reset (por='xxxxxxxx' mclr='uuuuuuuu')
    bit (names='CAP2BUFH' width='8')
    stimulus (scl=rwb regfiles=w)
sfr (key=CAP1BUFL addr=0xf68 size=1 access='rw rw rw rw rw rw rw rw')
    reset (por='xxxxxxxx' mclr='uuuuuuuu')
    bit (names='CAP1BUFL' width='8')
    stimulus (scl=rwb regfiles=w)
sfr (key=CAP1BUFH addr=0xf69 size=1 access='rw rw rw rw rw rw rw rw')
    reset (por='xxxxxxxx' mclr='uuuuuuuu')
    bit (names='CAP1BUFH' width='8')
    stimulus (scl=rwb regfiles=w)
sfr (key=OVDCONS addr=0xf6a size=1 access='rw rw rw rw rw rw rw rw')
    reset (por='00000000' mclr='00000000')
    bit (names='POUT' width='8')
    stimulus (scl=rwb regfiles=w)
sfr (key=OVDCOND addr=0xf6b size=1 access='rw rw rw rw rw rw rw rw')
    reset (por='11111111' mclr='11111111')
    bit (names='POVD' width='8')
    stimulus (scl=rwb regfiles=w)
sfr (key=FLTCONFIG addr=0xf6c size=1 access='rw rw rw rw rw rw rw rw')
    reset (por='00000000' mclr='00000000')
    bit (names='BRFEN FLTBS FLTBMOD FLTBEN FLTCON FLTAS FLTAMOD FLTAEN' width='1 1 1 1 1 1 1 1')
    stimulus (scl=rwb regfiles=w)
sfr (key=DTCON addr=0xf6d size=1 access='rw rw rw rw rw rw rw rw')
    reset (por='00000000' mclr='00000000')
    bit (names='DTAPS DTA' width='2 6')
    stimulus (scl=rwb regfiles=w)
sfr (key=PWMCON1 addr=0xf6e size=1 access='rw rw rw rw rw u rw rw')
    reset (por='00000-00' mclr='00000-00')
    bit (names='SEVOPS SEVTDIR - UDIS OSYNC' width='4 1 1 1 1')
    stimulus (scl=rwb regfiles=w)
sfr (key=PWMCON0 addr=0xf6f size=1 access='u rw rw rw rw rw rw rw')
    reset (por='-1010000' mclr='-1010000')
    bit (names='- PWMEN PMOD' width='1 3 4')
    stimulus (scl=rwb regfiles=w)
sfr (key=SEVTCMPH addr=0xf70 size=1 access='u u u u rw rw rw rw')
    reset (por='----0000' mclr='----0000')
    bit (names='- - - - SEVTCMPH' width='1 1 1 1 4')
    stimulus (scl=rwb regfiles=w)
sfr (key=SEVTCMPL addr=0xf71 size=1 access='rw rw rw rw rw rw rw rw')
    reset (por='00000000' mclr='00000000')
    bit (names='SEVTCMPL' width='8')
    stimulus (scl=rwb regfiles=w)
UnusedRegs (0xf72-0xf73)
sfr (key=PDC2H addr=0xf74 size=1 access='u u rw rw rw rw rw rw')
    reset (por='--000000' mclr='--000000')
    bit (names='- - PDC2H' width='1 1 6')
    stimulus (scl=rwb regfiles=w)
sfr (key=PDC2L addr=0xf75 size=1 access='rw rw rw rw rw rw rw rw')
    reset (por='00000000' mclr='00000000')
    bit (names='PDC2L' width='8')
    stimulus (scl=rwb regfiles=w)
sfr (key=PDC1H addr=0xf76 size=1 access='u u rw rw rw rw rw rw')
    reset (por='--000000' mclr='--000000')
    bit (names='- - PDC1H' width='1 1 6')
    stimulus (scl=rwb regfiles=w)
sfr (key=PDC1L addr=0xf77 size=1 access='rw rw rw rw rw rw rw rw')
    reset (por='00000000' mclr='00000000')
    bit (names='PDC1L' width='8')
    stimulus (scl=rwb regfiles=w)
sfr (key=PDC0H addr=0xf78 size=1 access='u u rw rw rw rw rw rw')
    reset (por='--000000' mclr='--000000')
    bit (names='- - PDC0H' width='1 1 6')
    stimulus (scl=rwb regfiles=w)
sfr (key=PDC0L addr=0xf79 size=1 access='rw rw rw rw rw rw rw rw')
    reset (por='00000000' mclr='00000000')
    bit (names='PDC0L' width='8')
    stimulus (scl=rwb regfiles=w)
sfr (key=PTPERH addr=0xf7a size=1 access='u u u u rw rw rw rw')
    reset (por='----1111' mclr='----1111')
    bit (names='- - - - PTPERH' width='1 1 1 1 4')
    stimulus (scl=rwb regfiles=w)
sfr (key=PTPERL addr=0xf7b size=1 access='rw rw rw rw rw rw rw rw')
    reset (por='11111111' mclr='11111111')
    bit (names='PTPERL' width='8')
    stimulus (scl=rwb regfiles=w)
sfr (key=PTMRH addr=0xf7c size=1 access='u u u u rw rw rw rw')
    reset (por='----0000' mclr='----0000')
    bit (names='- - - - PTMRH' width='1 1 1 1 4')
    stimulus (scl=rwb regfiles=w)
sfr (key=PTMRL addr=0xf7d size=1 access='rw rw rw rw rw rw rw rw')
    reset (por='00000000' mclr='00000000')
    bit (names='PTMRL' width='8')
    stimulus (scl=rwb regfiles=w)
sfr (key=PTCON1 addr=0xf7e size=1 access='rw r u u u u u u')
    reset (por='00------' mclr='00------')
    bit (names='PTEN PTDIR - - - - - -' width='1 1 1 1 1 1 1 1')
    stimulus (scl=rwb regfiles=w)
sfr (key=PTCON0 addr=0xf7f size=1 access='rw rw rw rw rw rw rw rw')
    reset (por='00000000' mclr='uuuuuuuu')
    bit (names='PTOPS PTCKPS PTMOD' width='4 2 2')
    stimulus (scl=rwb regfiles=w)
sfr (key=PORTA addr=0xf80 size=1 access='rw rw u rw rw rw rw rw')
    reset (por='xx-00000' mclr='uu-00000')
    bit (names='RA7 RA6 - RA4 RA3 RA2 RA1 RA0' width='1 1 1 1 1 1 1 1')
    bit (tag=scl names='RA' width='8')
    stimulus (scl=rwb pcfiles=rw regfiles=rw)
sfr (key=PORTB addr=0xf81 size=1 access='rw rw rw rw rw rw rw rw')
    reset (por='xxxxxxxx' mclr='uuuuuuuu')
    bit (names='RB7 RB6 RB5 RB4 RB3 RB2 RB1 RB0' width='1 1 1 1 1 1 1 1')
    bit (tag=scl names='RB' width='8')
    stimulus (scl=rwb pcfiles=rw regfiles=rw)
sfr (key=PORTC addr=0xf82 size=1 access='rw rw rw rw rw rw rw rw')
    reset (por='xxxxxxxx' mclr='uuuuuuuu')
    bit (names='RC7 RC6 RC5 RC4 RC3 RC2 RC1 RC0' width='1 1 1 1 1 1 1 1')
    bit (tag=scl names='RC' width='8')
    stimulus (scl=rwb pcfiles=rw regfiles=rw)
UnusedRegs (0xf83-0xf83)
sfr (key=PORTE addr=0xf84 size=1 access='u u u u r u u u')
    reset (por='----x---' mclr='----u---')
    bit (names='- - - - RE3 - - -' width='1 1 1 1 1 1 1 1')
    bit (tag=scl names='RE' width='8')
    stimulus (scl=rwb pcfiles=r regfiles=r)
UnusedRegs (0xf85-0xf86)
sfr (key=TMR5 addr=0xf87 size=2 flags=j)
    bit (names='TMR5' width='16')
sfr (key=TMR5L addr=0xf87 size=1 access='rw rw rw rw rw rw rw rw')
    reset (por='xxxxxxxx' mclr='uuuuuuuu')
    bit (names='TMR5L' width='8')
    stimulus (scl=rwb pcfiles=w regfiles=w type=int)
sfr (key=TMR5H addr=0xf88 size=1 access='rw rw rw rw rw rw rw rw')
    reset (por='xxxxxxxx' mclr='uuuuuuuu')
    bit (names='TMR5H' width='8')
    stimulus (scl=rwb pcfiles=w regfiles=w type=int)
sfr (key=LATA addr=0xf89 size=1 access='rw rw u rw rw rw rw rw')
    reset (por='xxxxxxxx' mclr='uuuuuuuu')
    bit (names='LATA7 LATA6 - LATA4 LATA3 LATA2 LATA1 LATA0' width='1 1 1 1 1 1 1 1')
    bit (tag=scl names='LATA' width='8')
    stimulus (scl=rwb regfiles=w)
sfr (key=LATB addr=0xf8a size=1 access='rw rw rw rw rw rw rw rw')
    reset (por='xxxxxxxx' mclr='uuuuuuuu')
    bit (names='LATB7 LATB6 LATB5 LATB4 LATB3 LATB2 LATB1 LATB0' width='1 1 1 1 1 1 1 1')
    bit (tag=scl names='LATB' width='8')
    stimulus (scl=rwb regfiles=w)
sfr (key=LATC addr=0xf8b size=1 access='rw rw rw rw rw rw rw rw')
    reset (por='xxxxxxxx' mclr='uuuuuuuu')
    bit (names='LATC7 LATC6 LATC5 LATC4 LATC3 LATC2 LATC1 LATC0' width='1 1 1 1 1 1 1 1')
    bit (tag=scl names='LATC' width='8')
    stimulus (scl=rwb regfiles=w)
UnusedRegs (0xf8c-0xf8f)
sfr (key=PR5 addr=0xf90 size=2 flags=j)
    bit (names='PR5' width='16')
sfr (key=PR5L addr=0xf90 size=1 access='rw rw rw rw rw rw rw rw')
    reset (por='11111111' mclr='11111111')
    bit (names='PR5L' width='8')
    stimulus (scl=rwb regfiles=w type=int)
sfr (key=PR5H addr=0xf91 size=1 access='rw rw rw rw rw rw rw rw')
    reset (por='11111111' mclr='11111111')
    bit (names='PR5H' width='8')
    stimulus (scl=rwb regfiles=w type=int)
sfr (key=TRISA addr=0xf92 size=1 access='rw rw u rw rw rw rw rw')
    reset (por='11-11111' mclr='11-11111')
    bit (names='TRISA7 TRISA6 - TRISA4 TRISA3 TRISA2 TRISA1 TRISA0' width='1 1 1 1 1 1 1 1')
    bit (tag=scl names='TRISA' width='8')
    stimulus (scl=rwb regfiles=w)
sfr (key=TRISB addr=0xf93 size=1 access='rw rw rw rw rw rw rw rw')
    reset (por='11111111' mclr='11111111')
    bit (names='TRISB7 TRISB6 TRISB5 TRISB4 TRISB3 TRISB2 TRISB1 TRISB0' width='1 1 1 1 1 1 1 1')
    bit (tag=scl names='TRISB' width='8')
    stimulus (scl=rwb regfiles=w)
sfr (key=TRISC addr=0xf94 size=1 access='rw rw rw rw rw rw rw rw')
    reset (por='11111111' mclr='11111111')
    bit (names='TRISC7 TRISC6 TRISC5 TRISC4 TRISC3 TRISC2 TRISC1 TRISC0' width='1 1 1 1 1 1 1 1')
    bit (tag=scl names='TRISC' width='8')
    stimulus (scl=rwb regfiles=w)
UnusedRegs (0xf95-0xf98)
sfr (key=ADCHS addr=0xf99 size=1 access='rw rw rw rw rw rw rw rw')
    reset (por='00000000' mclr='00000000')
    bit (names='SDSEL SBSEL SCSEL SASEL' width='2 2 2 2')
    stimulus (scl=rwb regfiles=w)
sfr (key=ADCON3 addr=0xf9a size=1 access='rw rw u rw rw rw rw rw')
    reset (por='00-00000' mclr='00-00000')
    bit (names='ADRS - SSRC' width='2 1 5')
    stimulus (scl=rwb regfiles=w)
sfr (key=OSCTUNE addr=0xf9b size=1 access='u u rw rw rw rw rw rw')
    reset (por='--000000' mclr='--000000')
    bit (names='- - TUN' width='1 1 6')
UnusedRegs (0xf9c-0xf9c)
sfr (key=PIE1 addr=0xf9d size=1 access='u rw rw rw rw rw rw rw')
    reset (por='-0000000' mclr='-0000000')
    bit (names='- ADIE RCIE TXIE SSPIE CCP1IE TMR2IE TMR1IE' width='1 1 1 1 1 1 1 1')
    stimulus (scl=rwb pcfiles=rw regfiles=w)
sfr (key=PIR1 addr=0xf9e size=1 access='u rw r r rw rw rw rw')
    reset (por='-0000000' mclr='-0000000')
    bit (names='- ADIF RCIF TXIF SSPIF CCP1IF TMR2IF TMR1IF' width='1 1 1 1 1 1 1 1')
    bit (tag=scl names='- ADIF - - SSPIF CCP1IF TMR2IF TMR1IF' width='1 1 1 1 1 1 1 1')
    stimulus (scl=rwb pcfiles=rw regfiles=w)
sfr (key=IPR1 addr=0xf9f size=1 access='u rw rw rw rw rw rw rw')
    reset (por='-1111111' mclr='-1111111')
    bit (names='- ADIP RCIP TXIP SSPIP CCP1IP TMR2IP TMR1IP' width='1 1 1 1 1 1 1 1')
    stimulus (scl=rwb pcfiles=rw regfiles=w)
sfr (key=PIE2 addr=0xfa0 size=1 access='rw u u rw u rw u rw')
    reset (por='0--0-0-0' mclr='0--0-0-0')
    bit (names='OSFIE - - EEIE - LVDIE - CCP2IE' width='1 1 1 1 1 1 1 1')
    stimulus (scl=rwb pcfiles=rw regfiles=w)
sfr (key=PIR2 addr=0xfa1 size=1 access='rw u u rw u rw u rw')
    reset (por='0--0-0-0' mclr='0--0-0-0')
    bit (names='OSFIF - - EEIF - LVDIF - CCP2IF' width='1 1 1 1 1 1 1 1')
    stimulus (scl=rwb pcfiles=rw regfiles=w)
sfr (key=IPR2 addr=0xfa2 size=1 access='rw u u rw u rw u rw')
    reset (por='1--1-1-1' mclr='1--1-1-1')
    bit (names='OSFIP - - EEIP - LVDIP - CCP2IP' width='1 1 1 1 1 1 1 1')
    stimulus (scl=rwb pcfiles=rw regfiles=w)
sfr (key=PIE3 addr=0xfa3 size=1 access='u u u rw rw rw rw rw')
    reset (por='---00000' mclr='---00000')
    bit (names='- - - PTIE IC3DRIE IC2QEIE IC1IE TMR5IE' width='1 1 1 1 1 1 1 1')
    stimulus (scl=rwb pcfiles=rw regfiles=w)
sfr (key=PIR3 addr=0xfa4 size=1 access='u u u rw rw rw rw rw')
    reset (por='---00000' mclr='---00000')
    bit (names='- - - PTIF IC3DRIF IC2QEIF IC1IF TMR5IF' width='1 1 1 1 1 1 1 1')
    stimulus (scl=rwb pcfiles=rw regfiles=w)
sfr (key=IPR3 addr=0xfa5 size=1 access='u u u rw rw rw rw rw')
    reset (por='---11111' mclr='---11111')
    bit (names='- - - PTIP IC3DRIP IC2QEIP IC1IP TMR5IP' width='1 1 1 1 1 1 1 1')
    stimulus (scl=rwb pcfiles=rw regfiles=w)
sfr (key=EECON1 addr=0xfa6 size=1 access='rw rw u rw rw rw rs rs')
    reset (por='xx-0x000' mclr='uu-0u000')
    bit (names='EEPGD CFGS - FREE WRERR WREN WR RD' width='1 1 1 1 1 1 1 1')
    stimulus (scl=rwb pcfiles=rw regfiles=w)
sfr (key=EECON2 addr=0xfa7 size=1 access='w w w w w w w w')
    reset (por='--------' mclr='--------')
    bit (names='EECON2' width='8')
sfr (key=EEDATA addr=0xfa8 size=1 access='rw rw rw rw rw rw rw rw')
    reset (por='xxxxxxxx' mclr='uuuuuuuu')
    bit (names='EEDATA' width='8')
    stimulus (scl=rwb pcfiles=rw regfiles=rw)
sfr (key=EEADR addr=0xfa9 size=1 access='rw rw rw rw rw rw rw rw')
    reset (por='xxxxxxxx' mclr='uuuuuuuu')
    bit (names='EEADR' width='8')
    stimulus (scl=rwb pcfiles=rw regfiles=w)
sfr (key=BAUDCON addr=0xfaa size=1 access='rc r rw rw rw u rw rw')
    reset (por='01000-00' mclr='01000-00')
    bit (names='ABDOVF RCIDL RXDTP TXCKP BRG16 - WUE ABDEN' width='1 1 1 1 1 1 1 1')
    stimulus (scl=rwb regfiles=w)
sfr (key=RCSTA addr=0xfab size=1 access='rw rw rw rw rw r r r')
    reset (por='0000000x' mclr='0000000x')
    bit (names='SPEN RX9 SREN CREN ADDEN FERR OERR RX9D' width='1 1 1 1 1 1 1 1')
    stimulus (scl=rwb regfiles=w)
sfr (key=TXSTA addr=0xfac size=1 access='rw rw rw rw rw rw r rw')
    reset (por='00000010' mclr='00000010')
    bit (names='CSRC TX9 TXEN SYNC SENDB BRGH TRMT TX9D' width='1 1 1 1 1 1 1 1')
    stimulus (scl=rwb regfiles=w)
sfr (key=TXREG addr=0xfad size=1 access='w w w w w w w w')
    reset (por='00000000' mclr='00000000')
    bit (names='TXREG' width='8')
    stimulus (scl=rwb regfiles=w)
sfr (key=RCREG addr=0xfae size=1 access='r r r r r r r r')
    reset (por='00000000' mclr='00000000')
    bit (names='RCREG' width='8')
    stimulus (scl=rb regfiles=rp)
sfr (key=SPBRG addr=0xfaf size=1 access='rw rw rw rw rw rw rw rw')
    reset (por='00000000' mclr='00000000')
    bit (names='SPBRG' width='8')
    stimulus (scl=rwb regfiles=w)
sfr (key=SPBRGH addr=0xfb0 size=1 access='rw rw rw rw rw rw rw rw')
    reset (por='00000000' mclr='00000000')
    bit (names='SPBRGH' width='8')
    stimulus (scl=rwb regfiles=w)
UnusedRegs (0xfb1-0xfb5)
sfr (key=QEICON addr=0xfb6 size=1 access='rw rw rw rw rw rw rw rw')
    reset (por='00000000' mclr='00000000')
    bit (names='nVELM ERROR UP/nDOWN QEIM PDEC' width='1 1 1 3 2')
    bit (tag=scl names='nVELM - UP_nDOWN QEIM PDEC' width='1 1 1 3 2')
    stimulus (scl=rwb pcfiles=rw regfiles=w)
sfr (key=T5CON addr=0xfb7 size=1 access='rw rw rw rw rw rw rw rw')
    reset (por='00000000' mclr='00000000')
    bit (names='T5SEN nRESEN T5MOD T5PS nT5SYNC TMR5CS TMR5ON' width='1 1 1 2 1 1 1')
    stimulus (scl=rwb regfiles=w)
sfr (key=ANSEL0 addr=0xfb8 size=1 access='u u u rw rw rw rw rw')
    reset (por='---11111' mclr='---11111')
    bit (names='- - - ANS4 ANS3 ANS2 ANS1 ANS0' width='1 1 1 1 1 1 1 1')
    stimulus (scl=rwb regfiles=w)
UnusedRegs (0xfb9-0xfb9)
sfr (key=CCP2CON addr=0xfba size=1 access='u u rw rw rw rw rw rw')
    reset (por='--000000' mclr='--000000')
    bit (names='- - DC2B CCP2M' width='1 1 2 4')
    stimulus (scl=rwb regfiles=w)
sfr (key=CCPR2 addr=0xfbb size=2 flags=j)
    bit (names='CCPR2' width='16')
sfr (key=CCPR2L addr=0xfbb size=1 access='rw rw rw rw rw rw rw rw')
    reset (por='xxxxxxxx' mclr='uuuuuuuu')
    bit (names='CCPR2L' width='8')
    stimulus (scl=rwb regfiles=w type=int)
sfr (key=CCPR2H addr=0xfbc size=1 access='rw rw rw rw rw rw rw rw')
    reset (por='xxxxxxxx' mclr='uuuuuuuu')
    bit (names='CCPR2H' width='8')
    stimulus (scl=rwb regfiles=w type=int)
sfr (key=CCP1CON addr=0xfbd size=1 access='u u rw rw rw rw rw rw')
    reset (por='--000000' mclr='--000000')
    bit (names='- - DC1B CCP1M' width='1 1 2 4')
    stimulus (scl=rwb regfiles=w)
sfr (key=CCPR1 addr=0xfbe size=2 flags=j)
    bit (names='CCPR1' width='16')
sfr (key=CCPR1L addr=0xfbe size=1 access='rw rw rw rw rw rw rw rw')
    reset (por='xxxxxxxx' mclr='uuuuuuuu')
    bit (names='CCPR1L' width='8')
    stimulus (scl=rwb regfiles=w type=int)
sfr (key=CCPR1H addr=0xfbf size=1 access='rw rw rw rw rw rw rw rw')
    reset (por='xxxxxxxx' mclr='uuuuuuuu')
    bit (names='CCPR1H' width='8')
    stimulus (scl=rwb regfiles=w type=int)
sfr (key=ADCON2 addr=0xfc0 size=1 access='rw rw rw rw rw rw rw rw')
    reset (por='00000000' mclr='00000000')
    bit (names='ADFM ACQT ADCS' width='1 4 3')
    stimulus (scl=rwb regfiles=w)
sfr (key=ADCON1 addr=0xfc1 size=1 access='rw rw u rw r r r r')
    reset (por='00-00000' mclr='00-00000')
    bit (names='VCFG - FIFOEN BFEMT BFOVFL ADPNT' width='2 1 1 1 1 2')
    stimulus (scl=rwb regfiles=w)
sfr (key=ADCON0 addr=0xfc2 size=1 access='u u rw rw rw rw rw rw')
    reset (por='--000000' mclr='--000000')
    bit (names='- - ACONV ACSCH ACMOD GO/nDONE ADON' width='1 1 1 1 2 1 1')
    bit (tag=scl names='- - ACONV ACSCH ACMOD GO_nDONE ADON' width='1 1 1 1 2 1 1')
    stimulus (scl=rwb regfiles=w)
sfr (key=ADRES addr=0xfc3 size=2 flags=j)
    bit (names='ADRES' width='16')
sfr (key=ADRESL addr=0xfc3 size=1 access='rw rw rw rw rw rw rw rw')
    reset (por='xxxxxxxx' mclr='uuuuuuuu')
    bit (names='ADRESL' width='8')
    stimulus (scl=rwb regfiles=r type=int)
sfr (key=ADRESH addr=0xfc4 size=1 access='rw rw rw rw rw rw rw rw')
    reset (por='xxxxxxxx' mclr='uuuuuuuu')
    bit (names='ADRESH' width='8')
    stimulus (scl=rwb regfiles=w type=int)
UnusedRegs (0xfc5-0xfc5)
sfr (key=SSPCON addr=0xfc6 size=1 access='rw rw rw rw rw rw rw rw')
    reset (por='00000000' mclr='00000000')
    bit (names='WCOL SSPOV SSPEN CKP SSPM' width='1 1 1 1 4')
    stimulus (scl=rwb pcfiles=rw regfiles=w)
sfr (key=SSPSTAT addr=0xfc7 size=1 access='rw rw rw rw rw rw rw rw')
    reset (por='00000000' mclr='00000000')
    bit (names='SMP CKE D/nA P S R/nW UA BF' width='1 1 1 1 1 1 1 1')
    bit (tag=scl names='SMP CKE D_nA P S R_nW UA BF' width='1 1 1 1 1 1 1 1')
    stimulus (scl=rwb pcfiles=rw regfiles=rw)
sfr (key=SSPADD addr=0xfc8 size=1 access='rw rw rw rw rw rw rw rw')
    reset (por='00000000' mclr='00000000')
    bit (names='SSPADD' width='8')
    stimulus (scl=rwb pcfiles=rw regfiles=w)
sfr (key=SSPBUF addr=0xfc9 size=1 access='rw rw rw rw rw rw rw rw')
    reset (por='xxxxxxxx' mclr='uuuuuuuu')
    bit (names='SSPBUF' width='8')
    stimulus (scl=rwb pcfiles=rw regfiles=rw)
sfr (key=T2CON addr=0xfca size=1 access='u rw rw rw rw rw rw rw')
    reset (por='-0000000' mclr='-0000000')
    bit (names='- TOUTPS TMR2ON T2CKPS' width='1 4 1 2')
    stimulus (scl=rwb regfiles=w)
sfr (key=PR2 addr=0xfcb size=1 access='rw rw rw rw rw rw rw rw')
    reset (por='11111111' mclr='11111111')
    bit (names='PR2' width='8')
    stimulus (scl=rwb regfiles=w type=int)
sfr (key=TMR2 addr=0xfcc size=1 access='rw rw rw rw rw rw rw rw')
    reset (por='00000000' mclr='00000000')
    bit (names='TMR2' width='8')
    stimulus (scl=rwb pcfiles=w regfiles=w type=int)
sfr (key=T1CON addr=0xfcd size=1 access='rw rw rw rw r r rw rw')
    reset (por='00000000' mclr='u0uuuuuu')
    bit (names='RD16 T1RUN T1CKPS T1OSCEN nT1SYNC TMR1CS TMR1ON' width='1 1 2 1 1 1 1')
    stimulus (scl=rwb regfiles=w)
sfr (key=TMR1 addr=0xfce size=2 flags=j)
    bit (names='TMR1' width='16')
sfr (key=TMR1L addr=0xfce size=1 access='rw rw rw rw rw rw rw rw')
    reset (por='xxxxxxxx' mclr='uuuuuuuu')
    bit (names='TMR1L' width='8')
    stimulus (scl=rwb pcfiles=w regfiles=w type=int)
sfr (key=TMR1H addr=0xfcf size=1 access='rw rw rw rw rw rw rw rw')
    reset (por='xxxxxxxx' mclr='uuuuuuuu')
    bit (names='TMR1H' width='8')
    stimulus (scl=rwb pcfiles=w regfiles=w type=int)
sfr (key=RCON addr=0xfd0 size=1 access='rw u u rw rw rw rw rw')
    reset (por='0--111qq' mclr='0--qqquu')
    bit (names='IPEN - - nRI nTO nPD nPOR nBOR' width='1 1 1 1 1 1 1 1')
    stimulus (scl=r pcfiles=rw regfiles=w)
sfr (key=WDTCON addr=0xfd1 size=1 access='r u u u u u u rw')
    reset (por='00000000' mclr='00000000')
    bit (names='WDTW - - - - - - SWDTEN' width='1 1 1 1 1 1 1 1')
    stimulus (scl=rwb pcfiles=rw regfiles=w)
sfr (key=LVDCON addr=0xfd2 size=1 access='u u rw rw rw rw rw rw')
    reset (por='--000101' mclr='--000101')
    bit (names='- - IRVST LVDEN LVDL' width='1 1 1 1 4')
    stimulus (scl=rwb pcfiles=rw regfiles=w)
sfr (key=OSCCON addr=0xfd3 size=1 access='rw rw rw rw r r rw rw')
    reset (por='00000000' mclr='00000000')
    bit (names='IDLEN IRCF OSTS IOFS SCS' width='1 3 1 1 2')
    stimulus (scl=rwb pcfiles=rw regfiles=w)
UnusedRegs (0xfd4-0xfd4)
sfr (key=T0CON addr=0xfd5 size=1 access='rw rw rw rw rw rw rw rw')
    reset (por='11111111' mclr='11111111')
    bit (names='TMR0ON T016BIT T0CS T0SE PSA T0PS' width='1 1 1 1 1 3')
    stimulus (scl=rwb regfiles=w)
sfr (key=TMR0 addr=0xfd6 size=2 flags=j)
    bit (names='TMR0' width='16')
sfr (key=TMR0L addr=0xfd6 size=1 access='rw rw rw rw rw rw rw rw')
    reset (por='xxxxxxxx' mclr='uuuuuuuu')
    bit (names='TMR0L' width='8')
    stimulus (scl=rwb pcfiles=w regfiles=w type=int)
sfr (key=TMR0H addr=0xfd7 size=1 access='rw rw rw rw rw rw rw rw')
    reset (por='00000000' mclr='00000000')
    bit (names='TMR0H' width='8')
    stimulus (scl=rwb pcfiles=w regfiles=w type=int)
sfr (key=STATUS addr=0xfd8 size=1 access='u u u rw rw rw rw rw')
    reset (por='---xxxxx' mclr='---uuuuu')
    bit (names='- - - N OV Z DC C' width='1 1 1 1 1 1 1 1')
sfr (key=FSR2 addr=0xfd9 size=2 flags=j)
    bit (names='- - - - FSR2' width='1 1 1 1 12')
sfr (key=FSR2L addr=0xfd9 size=1 access='rw rw rw rw rw rw rw rw')
    reset (por='xxxxxxxx' mclr='uuuuuuuu')
    bit (names='FSR2L' width='8')
    stimulus (scl=rwb pcfiles=rw regfiles=w)
sfr (key=FSR2H addr=0xfda size=1 access='u u u u rw rw rw rw')
    reset (por='----0000' mclr='----0000')
    bit (names='- - - - FSR2H' width='1 1 1 1 4')
    stimulus (scl=rwb pcfiles=rw regfiles=w)
sfr (key=PLUSW2 addr=0xfdb size=1 flags=i access='u u u u u u u u')
    reset (por='--------' mclr='--------')
    bit (names='PLUSW2' width='8')
sfr (key=PREINC2 addr=0xfdc size=1 flags=i access='u u u u u u u u')
    reset (por='--------' mclr='--------')
    bit (names='PREINC2' width='8')
sfr (key=POSTDEC2 addr=0xfdd size=1 flags=i access='u u u u u u u u')
    reset (por='--------' mclr='--------')
    bit (names='POSTDEC2' width='8')
sfr (key=POSTINC2 addr=0xfde size=1 flags=i access='u u u u u u u u')
    reset (por='--------' mclr='--------')
    bit (names='POSTINC2' width='8')
sfr (key=INDF2 addr=0xfdf size=1 flags=i access='u u u u u u u u')
    reset (por='--------' mclr='--------')
    bit (names='INDF2' width='8')
sfr (key=BSR addr=0xfe0 size=1 access='u u u u rw rw rw rw')
    reset (por='----0000' mclr='----0000')
    bit (names='- - - - BSR' width='1 1 1 1 4')
    stimulus (scl=rwb pcfiles=rw regfiles=w)
sfr (key=FSR1 addr=0xfe1 size=2 flags=j)
    bit (names='- - - - FSR1' width='1 1 1 1 12')
sfr (key=FSR1L addr=0xfe1 size=1 access='rw rw rw rw rw rw rw rw')
    reset (por='xxxxxxxx' mclr='uuuuuuuu')
    bit (names='FSR1L' width='8')
    stimulus (scl=rwb pcfiles=rw regfiles=w)
sfr (key=FSR1H addr=0xfe2 size=1 access='u u u u rw rw rw rw')
    reset (por='----0000' mclr='----uuuu')
    bit (names='- - - - FSR1H' width='1 1 1 1 4')
    stimulus (scl=rwb pcfiles=rw regfiles=w)
sfr (key=PLUSW1 addr=0xfe3 size=1 flags=i access='u u u u u u u u')
    reset (por='--------' mclr='--------')
    bit (names='PLUSW1' width='8')
sfr (key=PREINC1 addr=0xfe4 size=1 flags=i access='u u u u u u u u')
    reset (por='--------' mclr='--------')
    bit (names='PREINC1' width='8')
sfr (key=POSTDEC1 addr=0xfe5 size=1 flags=i access='u u u u u u u u')
    reset (por='--------' mclr='--------')
    bit (names='POSTDEC1' width='8')
sfr (key=POSTINC1 addr=0xfe6 size=1 flags=i access='u u u u u u u u')
    reset (por='--------' mclr='--------')
    bit (names='POSTINC1' width='8')
sfr (key=INDF1 addr=0xfe7 size=1 flags=i access='u u u u u u u u')
    reset (por='--------' mclr='--------')
    bit (names='INDF1' width='8')
sfr (key=WREG addr=0xfe8 size=1 access='rw rw rw rw rw rw rw rw')
    reset (por='xxxxxxxx' mclr='uuuuuuuu')
    bit (names='WREG' width='8')
    stimulus (scl=rwb pcfiles=rw regfiles=w type=int)
sfr (key=FSR0 addr=0xfe9 size=2 flags=j)
    bit (names='- - - - FSR0' width='1 1 1 1 12')
sfr (key=FSR0L addr=0xfe9 size=1 access='rw rw rw rw rw rw rw rw')
    reset (por='xxxxxxxx' mclr='uuuuuuuu')
    bit (names='FSR0L' width='8')
    stimulus (scl=rwb pcfiles=rw regfiles=w)
sfr (key=FSR0H addr=0xfea size=1 access='u u u u rw rw rw rw')
    reset (por='----0000' mclr='----uuuu')
    bit (names='- - - - FSR0H' width='1 1 1 1 4')
    stimulus (scl=rwb pcfiles=rw regfiles=w)
sfr (key=PLUSW0 addr=0xfeb size=1 flags=i access='u u u u u u u u')
    reset (por='--------' mclr='--------')
    bit (names='PLUSW0' width='8')
sfr (key=PREINC0 addr=0xfec size=1 flags=i access='u u u u u u u u')
    reset (por='--------' mclr='--------')
    bit (names='PREINC0' width='8')
sfr (key=POSTDEC0 addr=0xfed size=1 flags=i access='u u u u u u u u')
    reset (por='--------' mclr='--------')
    bit (names='POSTDEC0' width='8')
sfr (key=POSTINC0 addr=0xfee size=1 flags=i access='u u u u u u u u')
    reset (por='--------' mclr='--------')
    bit (names='POSTINC0' width='8')
sfr (key=INDF0 addr=0xfef size=1 flags=i access='u u u u u u u u')
    reset (por='--------' mclr='--------')
    bit (names='INDF0' width='8')
sfr (key=INTCON3 addr=0xff0 size=1 access='rw rw u rw rw u rw rw')
    reset (por='11-00-00' mclr='11-00-00')
    bit (names='INT2IP INT1IP - INT2IE INT1IE - INT2IF INT1IF' width='1 1 1 1 1 1 1 1')
    stimulus (scl=rwb pcfiles=rw regfiles=w)
sfr (key=INTCON2 addr=0xff1 size=1 access='rw rw rw rw u rw u rw')
    reset (por='1111-1-1' mclr='1111-1-1')
    bit (names='nRBPU INTEDG0 INTEDG1 INTEDG2 - TMR0IP - RBIP' width='1 1 1 1 1 1 1 1')
    stimulus (scl=rwb pcfiles=rw regfiles=w)
sfr (key=INTCON addr=0xff2 size=1 access='rw rw rw rw rw rw rw rw')
    reset (por='0000000x' mclr='0000000u')
    bit (names='GIE/GIEH PEIE/GIEL TMR0IE INT0IE RBIE TMR0IF INT0IF RBIF' width='1 1 1 1 1 1 1 1')
    # NOTE: When IPEN (bit 7) in the RCON register is 0 use the following bit names
    qbit (names='GIE PEIE TMR0IE INT0IE RBIE TMR0IF INT0IF RBIF' width='1 1 1 1 1 1 1 1')
    # NOTE: When IPEN (bit 7) in the RCON register is 1 use the following bit names
    qbit (names='GIEH GIEL TMR0IE INT0IE RBIE TMR0IF INT0IF RBIF' width='1 1 1 1 1 1 1 1')
    bit (tag=scl names='GIE_GIEH PEIE_GIEL TMR0IE INT0IE RBIE TMR0IF INT0IF RBIF' width='1 1 1 1 1 1 1 1')
    stimulus (scl=rwb pcfiles=rw regfiles=w)
sfr (key=PROD addr=0xff3 size=2 flags=j)
    bit (names='PROD' width='16')
sfr (key=PRODL addr=0xff3 size=1 access='rw rw rw rw rw rw rw rw')
    reset (por='xxxxxxxx' mclr='uuuuuuuu')
    bit (names='PRODL' width='8')
    stimulus (scl=rwb pcfiles=rw regfiles=w)
sfr (key=PRODH addr=0xff4 size=1 access='rw rw rw rw rw rw rw rw')
    reset (por='xxxxxxxx' mclr='uuuuuuuu')
    bit (names='PRODH' width='8')
    stimulus (scl=rwb pcfiles=rw regfiles=w)
sfr (key=TABLAT addr=0xff5 size=1 access='rw rw rw rw rw rw rw rw')
    reset (por='00000000' mclr='00000000')
    bit (names='TABLAT' width='8')
    stimulus (scl=rwb pcfiles=rw regfiles=w)
sfr (key=TBLPTR addr=0xff6 size=3 flags=j)
    bit (names='- - ACSS TBLPTR' width='1 1 1 21')
sfr (key=TBLPTRL addr=0xff6 size=1 access='rw rw rw rw rw rw rw rw')
    reset (por='00000000' mclr='00000000')
    bit (names='TBLPTRL' width='8')
    stimulus (scl=rwb pcfiles=rw regfiles=w)
sfr (key=TBLPTRH addr=0xff7 size=1 access='rw rw rw rw rw rw rw rw')
    reset (por='00000000' mclr='00000000')
    bit (names='TBLPTRH' width='8')
    stimulus (scl=rwb pcfiles=rw regfiles=w)
sfr (key=TBLPTRU addr=0xff8 size=1 access='u u rw rw rw rw rw rw')
    reset (por='--000000' mclr='--000000')
    bit (names='- - ACSS TBLPTRU' width='1 1 1 5')
    stimulus (scl=rwb pcfiles=rw regfiles=w)
sfr (key=PCLAT addr=0xff9 size=3 flags=j)
    bit (names='- - - PCLAT' width='1 1 1 21')
sfr (key=PCL addr=0xff9 size=1 access='rw rw rw rw rw rw rw rw')
    reset (por='00000000' mclr='00000000')
    bit (names='PCL' width='8')
    stimulus (scl=rwb pcfiles=rw regfiles=w)
sfr (key=PCLATH addr=0xffa size=1 access='rw rw rw rw rw rw rw rw')
    reset (por='00000000' mclr='00000000')
    bit (names='PCH' width='8')
    stimulus (scl=rwb pcfiles=rw regfiles=w)
sfr (key=PCLATU addr=0xffb size=1 access='u u u rw rw rw rw rw')
    reset (por='---00000' mclr='---00000')
    bit (names='- - - PCU' width='1 1 1 5')
    stimulus (scl=rwb pcfiles=rw regfiles=w)
sfr (key=STKPTR addr=0xffc size=1 access='rc rc u rw rw rw rw rw')
    reset (por='00-00000' mclr='00-00000')
    bit (names='STKFUL STKUNF - STKPTR' width='1 1 1 5')
    stimulus (scl=rwb pcfiles=rw regfiles=w)
sfr (key=TOS addr=0xffd size=3 flags=j)
    bit (names='- - - TOS' width='1 1 1 21')
sfr (key=TOSL addr=0xffd size=1 access='rw rw rw rw rw rw rw rw')
    reset (por='00000000' mclr='00000000')
    bit (names='TOSL' width='8')
    stimulus (scl=rwb pcfiles=rw regfiles=w)
sfr (key=TOSH addr=0xffe size=1 access='rw rw rw rw rw rw rw rw')
    reset (por='00000000' mclr='00000000')
    bit (names='TOSH' width='8')
    stimulus (scl=rwb pcfiles=rw regfiles=w)
sfr (key=TOSU addr=0xfff size=1 access='u u u rw rw rw rw rw')
    reset (por='---00000' mclr='---00000')
    bit (names='- - - TOSU' width='1 1 1 5')
    stimulus (scl=rwb pcfiles=rw regfiles=w)

######################################################################
#
# Non Memory-Mapped Registers
#
# (Conditionally visible SFRs appear as NMMRs in the "Special Function
# Registers" section.)
#
######################################################################

HasNMMR=1
nmmr (key=TMR0_Internal addr=0xa size=2 access='r r r r r r r r r r r r r r r r')
    reset (por='xxxxxxxxxxxxxxxx' mclr='uuuuuuuuuuuuuuuu')
    bit (names='InternalTMR' width='16')
nmmr (key=TMR0_Prescale addr=0x12 size=1 access='rw rw rw rw rw rw rw rw')
    reset (por='xxxxxxxx' mclr='uuuuuuuu')
    bit (names='InternalPS' width='8')
nmmr (key=TMR1_Internal addr=0xc size=2 access='r r r r r r r r r r r r r r r r')
    reset (por='xxxxxxxxxxxxxxxx' mclr='uuuuuuuuuuuuuuuu')
    bit (names='InternalTMR' width='16')
nmmr (key=TMR1_Prescale addr=0x13 size=1 access='rw rw rw rw rw rw rw rw')
    reset (por='xxxxxxxx' mclr='uuuuuuuu')
    bit (names='InternalPS' width='8')
nmmr (key=TMR2_Prescale addr=0x14 size=1 access='rw rw rw rw rw rw rw rw')
    reset (por='xxxxxxxx' mclr='uuuuuuuu')
    bit (names='InternalPS' width='8')
nmmr (key=TMR5_Internal addr=0x10 size=2 access='r r r r r r r r r r r r r r r r')
    reset (por='xxxxxxxxxxxxxxxx' mclr='uuuuuuuuuuuuuuuu')
    bit (names='InternalTMR' width='16')
nmmr (key=TMR5_Prescale addr=0x17 size=1 access='rw rw rw rw rw rw rw rw')
    reset (por='xxxxxxxx' mclr='uuuuuuuu')
    bit (names='InternalPS' width='8')
NMMRObjSize=7

######################################################################
#
# Configuration Registers
#
######################################################################

cfgbits (key=CONFIG1H addr=0x300001 unused=0x0)
    field (key=OSC mask=0xf desc="Oscillator Selection bits")
        setting (req=0xc value=0xc desc="11XX External RC oscillator, CLKO function on RA6" freqmin=32000 freqmax=4000000)
        setting (req=0xe value=0xa desc="101X External RC oscillator, CLKO function on RA6" freqmin=32000 freqmax=4000000)
        setting (req=0xf value=0x9 desc="Internal oscillator block, CLKO function on RA6 and port function on RA7")
        setting (req=0xf value=0x8 desc="Internal oscillator block, port function on RA6 and port function on RA7")
        setting (req=0xf value=0x7 desc="External RC oscillator, port function on RA6" freqmin=32000 freqmax=4000000)
        setting (req=0xf value=0x6 desc="HS oscillator, PLL enabled (clock frequency = 4 x FOSC1)" freqmin=16000000 freqmax=40000000)
        setting (req=0xf value=0x5 desc="EC oscillator, port function on RA6" freqmin=32000 freqmax=40000000)
        setting (req=0xf value=0x4 desc="EC oscillator, CLKO function on RA6" freqmin=32000 freqmax=40000000)
        setting (req=0xf value=0x3 desc="External RC oscillator, CLKO function on RA6" freqmin=32000 freqmax=40000000)
        setting (req=0xf value=0x2 desc="HS oscillator" freqmin=4000000 freqmax=20000000)
        setting (req=0xf value=0x1 desc="XT oscillator" freqmin=1000000 freqmax=4000000)
        setting (req=0xf value=0x0 desc="LP oscillator" freqmin=32000 freqmax=200000)
    field (key=FCMEN mask=0x40 desc="Fail-Safe Clock Monitor Enable bit")
        setting (req=0x40 value=0x40 desc="Enabled")
        setting (req=0x40 value=0x0 desc="Disabled")
    field (key=IESO mask=0x80 desc="Internal External Oscillator Switchover bit")
        setting (req=0x80 value=0x80 desc="Enabled")
        setting (req=0x80 value=0x0 desc="Disabled")
cfgbits (key=CONFIG2L addr=0x300002 unused=0x0)
    illegal (mask=0xc value=0xc msg="Brown out voltage cannot be set to an undefined valued if Brown Out Detect is enabled")
    field (key=PWRTEN mask=0x1 desc="Power-up Timer Enable bit")
        setting (req=0x1 value=0x1 desc="Disabled")
        setting (req=0x1 value=0x0 desc="Enabled")
    field (key=BOREN mask=0x2 desc="Brown-out Reset Enable bits")
        setting (req=0x2 value=0x2 desc="Enabled")
        setting (req=0x2 value=0x0 desc="Disabled")
    field (key=BORV mask=0xc desc="Brown Out Reset Voltage bits")
        setting (req=0xc value=0xc desc="Reserved")
        setting (req=0xc value=0x8 desc="VBOR set to 2.7V")
        setting (req=0xc value=0x4 desc="VBOR set to 4.2V")
        setting (req=0xc value=0x0 desc="VBOR set to 4.5V")
cfgbits (key=CONFIG2H addr=0x300003 unused=0x0)
    field (key=WDTEN mask=0x1 desc="Watchdog Timer Enable bit" min=4)
        setting (req=0x1 value=0x1 desc="Enabled")
        setting (req=0x1 value=0x0 desc="Disabled")
    field (key=WDPS mask=0x1e desc="Watchdog Timer Postscale Select bits")
        setting (req=0x1e value=0x1e desc="1:32768")
        setting (req=0x1e value=0x1c desc="1:16384")
        setting (req=0x1e value=0x1a desc="1:8192")
        setting (req=0x1e value=0x18 desc="1:4096")
        setting (req=0x1e value=0x16 desc="1:2048")
        setting (req=0x1e value=0x14 desc="1:1024")
        setting (req=0x1e value=0x12 desc="1:512")
        setting (req=0x1e value=0x10 desc="1:256")
        setting (req=0x1e value=0xe desc="1:128")
        setting (req=0x1e value=0xc desc="1:64")
        setting (req=0x1e value=0xa desc="1:32")
        setting (req=0x1e value=0x8 desc="1:16")
        setting (req=0x1e value=0x6 desc="1:8")
        setting (req=0x1e value=0x4 desc="1:4")
        setting (req=0x1e value=0x2 desc="1:2")
        setting (req=0x1e value=0x0 desc="1:1")
    field (key=WINEN mask=0x20 desc="Watchdog Timer Window Enable bit")
        setting (req=0x20 value=0x20 desc="Disabled")
        setting (req=0x20 value=0x0 desc="Enabled")
cfgbits (key=CONFIG3L addr=0x300004 unused=0x0)
    field (key=PWMPIN mask=0x4 desc="PWM output pins Reset state control")
        setting (req=0x4 value=0x4 desc="Disabled")
        setting (req=0x4 value=0x0 desc="Enabled")
    field (key=LPOL mask=0x8 desc="Low-Side Transistors Polarity")
        setting (req=0x8 value=0x8 desc="PWM0, 2, 4 and 6 are active-high")
        setting (req=0x8 value=0x0 desc="PWM0, 2, 4 and 6 are active-low")
    field (key=HPOL mask=0x10 desc="High-Side Transistors Polarity")
        setting (req=0x10 value=0x10 desc="PWM1, 3, 5 and 7 are active-high")
        setting (req=0x10 value=0x0 desc="PWM1, 3, 5 and 7 are active-low")
    field (key=T1OSCMX mask=0x20 desc="Timer1 Oscillator MUX")
        setting (req=0x20 value=0x20 desc="Enabled")
        setting (req=0x20 value=0x0 desc="Disabled")
cfgbits (key=CONFIG3H addr=0x300005 unused=0x0)
    field (key=RES mask=0x1 desc="RESERVED" flags=xh)
        setting (req=0x1 value=0x1 desc="Maintain bit as 1.")
    field (key=RESERVED mask=0x1c desc="RESERVED" flags=xh)
        setting (req=0x1c value=0x1c desc="Maintain bits as 1s.")
    field (key=MCLRE mask=0x80 desc="MCLR Pin Enable bit")
        setting (req=0x80 value=0x80 desc="Enabled")
        setting (req=0x80 value=0x0 desc="Disabled")
cfgbits (key=CONFIG4L addr=0x300006 unused=0x0)
    field (key=STVREN mask=0x1 desc="Stack Full/Underflow Reset Enable bit")
        setting (req=0x1 value=0x1 desc="Enabled")
        setting (req=0x1 value=0x0 desc="Disabled")
    field (key=LVP mask=0x4 desc="Low-Voltage ICSP Enable bit")
        setting (req=0x4 value=0x4 desc="Enabled")
        setting (req=0x4 value=0x0 desc="Disabled")
    field (key=DEBUG mask=0x80 desc="Background Debugger Enable bit" flags=h)
        setting (req=0x80 value=0x80 desc="Disabled")
        setting (req=0x80 value=0x0 desc="Enabled")
cfgbits (key=CONFIG5L addr=0x300008 unused=0x0)
    field (key=CP0 mask=0x1 desc="Code Protection bit")
        setting (req=0x1 value=0x1 desc="Disabled")
            checksum (type=0x0 protregion=0x0-0x0)
        setting (req=0x1 value=0x0 desc="Enabled")
            checksum (type=0x27 protregion=0x200-0xfff)
    field (key=CP1 mask=0x2 desc="Code Protection bit")
        setting (req=0x2 value=0x2 desc="Disabled")
            checksum (type=0x0 protregion=0x0-0x0)
        setting (req=0x2 value=0x0 desc="Enabled")
            checksum (type=0x27 protregion=0x1000-0x1fff)
    field (key=RESERVED mask=0xc desc="RESERVED" flags=xh)
        setting (req=0xc value=0xc desc="Maintain bits as 1s.")
cfgbits (key=CONFIG5H addr=0x300009 unused=0x0)
    field (key=CPB mask=0x40 desc="Boot Block Code Protection bit")
        setting (req=0x40 value=0x40 desc="Disabled")
            checksum (type=0x0 protregion=0x0-0x0)
        setting (req=0x40 value=0x0 desc="Enabled")
            checksum (type=0x27 protregion=0x0-0x1ff)
    field (key=CPD mask=0x80 desc="Data EEPROM Code Protection bit")
        setting (req=0x80 value=0x80 desc="Disabled")
        setting (req=0x80 value=0x0 desc="Enabled")
cfgbits (key=CONFIG6L addr=0x30000a unused=0x0)
    field (key=WRT0 mask=0x1 desc="Write Protection bit")
        setting (req=0x1 value=0x1 desc="Disabled")
        setting (req=0x1 value=0x0 desc="Enabled")
    field (key=WRT1 mask=0x2 desc="Write Protection bit")
        setting (req=0x2 value=0x2 desc="Disabled")
        setting (req=0x2 value=0x0 desc="Enabled")
    field (key=RESERVED mask=0xc desc="RESERVED" flags=xh)
        setting (req=0xc value=0xc desc="Maintain bits as 1s.")
cfgbits (key=CONFIG6H addr=0x30000b unused=0x0)
    field (key=WRTC mask=0x20 desc="Configuration Register Write Protection bit")
        setting (req=0x20 value=0x20 desc="Disabled")
        setting (req=0x20 value=0x0 desc="Enabled")
    field (key=WRTB mask=0x40 desc="Boot Block Write Protection bit")
        setting (req=0x40 value=0x40 desc="Disabled")
        setting (req=0x40 value=0x0 desc="Enabled")
    field (key=WRTD mask=0x80 desc="Data EEPROM Write Protection bit")
        setting (req=0x80 value=0x80 desc="Disabled")
        setting (req=0x80 value=0x0 desc="Enabled")
cfgbits (key=CONFIG7L addr=0x30000c unused=0x0)
    field (key=EBTR0 mask=0x1 desc="Table Read Protection bit")
        setting (req=0x1 value=0x1 desc="Disabled")
        setting (req=0x1 value=0x0 desc="Enabled")
    field (key=EBTR1 mask=0x2 desc="Table Read Protection bit")
        setting (req=0x2 value=0x2 desc="Disabled")
        setting (req=0x2 value=0x0 desc="Enabled")
    field (key=RESERVED mask=0xc desc="RESERVED" flags=xh)
        setting (req=0xc value=0xc desc="Maintain bits as 1s.")
cfgbits (key=CONFIG7H addr=0x30000d unused=0x0)
    field (key=EBTRB mask=0x40 desc="Boot Block Table Read Protection bit")
        setting (req=0x40 value=0x40 desc="Disabled")
        setting (req=0x40 value=0x0 desc="Enabled")
