######################################################################
#
# MPLAB IDE .dev File Generated by `pic2dev.py'
#
# Device: PIC18LF45K50
# Family: 18xxxx
# Date: Tue Apr 30 09:46:49 2013
#
######################################################################


######################################################################
#
# Memory Regions & Other General Device Information
#
######################################################################

vpp (range=8.000-9.000 dflt=8.500)
vdd (range=1.800-3.600 dfltrange=2.700-3.600 nominal=3.300)
pgming (memtech=ee tries=1 lvpthresh=2.700 panelsize=0x0)
    wait (pgm=1000 eedata=4000 cfg=5000 userid=5000 erase=15000 lvpgm=1000 lverase=1000)
    latches (pgm=64 eedata=2 cfg=2 userid=8 rowerase=64)
HWStackDepth=31
breakpoints (numhwbp=3 datacapture=false idbyte=p)
testmem (region=0x200000-0x20047f)
userid (region=0x200000-0x200007)
cfgmem (region=0x300000-0x30000d)
devid (region=0x3ffffe-0x3fffff idmask=0xffe0 id=0x5c80)
    ver (id=0x5c80 desc="a0")
eedata (region=0x0-0xff)
bkbgvectmem (region=0x200028-0x200037)
pgmmem (region=0x0-0x7fff)
NumBanks=16
UnusedBankMask=0x7f00
AccessBankSplitOffset=0x60
UnusedRegs (0xf00-0xf52)

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#
# Special Function Registers
#
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UnusedRegs (0xf53-0xf56)
sfr (key=SRCON1 addr=0xf57 size=1 access='rw rw rw rw rw rw rw rw')
    reset (por='00000000' mclr='00000000')
    bit (names='SRSPE SRSCKE SRSC2E SRSC1E SRRPE SRRCKE SRRC2E SRRC1E' width='1 1 1 1 1 1 1 1')
sfr (key=SRCON0 addr=0xf58 size=1 access='rw rw rw rw rw rw rw rw')
    reset (por='00000000' mclr='00000000')
    bit (names='SRLEN SRCLK SRQEN SRNQEN SRPS SRPR' width='1 3 1 1 1 1')
sfr (key=CCPTMRS addr=0xf59 size=1 access='u u u u rw u u rw')
    reset (por='----0--0' mclr='----u--u')
    bit (names='- - - - C2TSEL - - C1TSEL' width='1 1 1 1 1 1 1 1')
UnusedRegs (0xf5a-0xf5a)
sfr (key=ANSELA addr=0xf5b size=1 access='u u rw u rw rw rw rw')
    reset (por='--1-1111' mclr='--1-1111')
    bit (names='- - ANSA5 - ANSA3 ANSA2 ANSA1 ANSA0' width='1 1 1 1 1 1 1 1')
    stimulus (scl=rwb pcfiles=rw regfiles=rw)
sfr (key=ANSELB addr=0xf5c size=1 access='u u rw rw rw rw rw rw')
    reset (por='--111111' mclr='--111111')
    bit (names='- - ANSB5 ANSB4 ANSB3 ANSB2 ANSB1 ANSB0' width='1 1 1 1 1 1 1 1')
    stimulus (scl=rwb pcfiles=rw regfiles=rw)
sfr (key=ANSELC addr=0xf5d size=1 access='rw rw u u u rw u u')
    reset (por='11---1--' mclr='11---1--')
    bit (names='ANSC7 ANSC6 - - - ANSC2 - -' width='1 1 1 1 1 1 1 1')
    stimulus (scl=rwb pcfiles=rw regfiles=rw)
sfr (key=ANSELD addr=0xf5e size=1 access='rw rw rw rw rw rw rw rw')
    reset (por='11111111' mclr='11111111')
    bit (names='ANSD7 ANSD6 ANSD5 ANSD4 ANSD3 ANSD2 ANSD1 ANSD0' width='1 1 1 1 1 1 1 1')
    stimulus (scl=rwb pcfiles=rw regfiles=rw)
sfr (key=ANSELE addr=0xf5f size=1 access='u u u u u rw rw rw')
    reset (por='-----111' mclr='-----111')
    bit (names='- - - - - ANSE2 ANSE1 ANSE0' width='1 1 1 1 1 1 1 1')
    stimulus (scl=rwb pcfiles=rw regfiles=rw)
sfr (key=UCON addr=0xf60 size=1 access='u rw r rc rw rw rw u')
    reset (por='-0x0000-' mclr='-0x0000-')
    bit (names='- PPBRST SE0 PKTDIS USBEN RESUME SUSPND -' width='1 1 1 1 1 1 1 1')
sfr (key=USTAT addr=0xf61 size=1 access='u r r r r r r u')
    reset (por='-xxxxxx-' mclr='-xxxxxx-')
    bit (names='- ENDP DIR PPBI -' width='1 4 1 1 1')
sfr (key=UCFG addr=0xf62 size=1 access='rw rw u rw rw rw rw rw')
    reset (por='00-00000' mclr='00-00000')
    bit (names='UTEYE UOEMON - UPUEN UTRDIS FSEN PPB' width='1 1 1 1 1 1 2')
sfr (key=UADDR addr=0xf63 size=1 access='u rw rw rw rw rw rw rw')
    reset (por='-0000000' mclr='-0000000')
    bit (names='- ADDR' width='1 7')
sfr (key=UIE addr=0xf64 size=1 access='u rw rw rw rw rw rw rw')
    reset (por='-0000000' mclr='-0000000')
    bit (names='- SOFIE STALLIE IDLEIE TRNIE ACTVIE UERRIE URSTIE' width='1 1 1 1 1 1 1 1')
sfr (key=UIR addr=0xf65 size=1 access='u rw rw rw rw rw r rw')
    reset (por='-0000000' mclr='-0000000')
    bit (names='- SOFIF STALLIF IDLEIF TRNIF ACTVIF UERRIF URSTIF' width='1 1 1 1 1 1 1 1')
sfr (key=UEIE addr=0xf66 size=1 access='rw u u rw rw rw rw rw')
    reset (por='0--00000' mclr='0--00000')
    bit (names='BTSEE - - BTOEE DFN8EE CRC16EE CRC5EE PIDEE' width='1 1 1 1 1 1 1 1')
sfr (key=UEIR addr=0xf67 size=1 access='rc u u rc rc rc rc rc')
    reset (por='0--00000' mclr='0--00000')
    bit (names='BTSEF - - BTOEF DFN8EF CRC16EF CRC5EF PIDEF' width='1 1 1 1 1 1 1 1')
sfr (key=UFRM addr=0xf68 size=2 flags=j)
sfr (key=UFRML addr=0xf68 size=1 access='r r r r r r r r')
    reset (por='xxxxxxxx' mclr='xxxxxxxx')
    bit (names='FRM' width='8')
    stimulus (scl=rwb regfiles=w)
sfr (key=UFRMH addr=0xf69 size=1 access='u u u u u r r r')
    reset (por='-----xxx' mclr='-----xxx')
    bit (names='- - - - - FRM' width='1 1 1 1 1 3')
    stimulus (scl=rwb regfiles=w)
sfr (key=UEP0 addr=0xf6a size=1 access='u u u rw rw rw rw rw')
    reset (por='---00000' mclr='---00000')
    bit (names='- - - EPHSHK EPCONDIS EPOUTEN EPINEN EPSTALL' width='1 1 1 1 1 1 1 1')
sfr (key=UEP1 addr=0xf6b size=1 access='u u u rw rw rw rw rw')
    reset (por='---00000' mclr='---00000')
    bit (names='- - - EPHSHK EPCONDIS EPOUTEN EPINEN EPSTALL' width='1 1 1 1 1 1 1 1')
sfr (key=UEP2 addr=0xf6c size=1 access='u u u rw rw rw rw rw')
    reset (por='---00000' mclr='---00000')
    bit (names='- - - EPHSHK EPCONDIS EPOUTEN EPINEN EPSTALL' width='1 1 1 1 1 1 1 1')
sfr (key=UEP3 addr=0xf6d size=1 access='u u u rw rw rw rw rw')
    reset (por='---00000' mclr='---00000')
    bit (names='- - - EPHSHK EPCONDIS EPOUTEN EPINEN EPSTALL' width='1 1 1 1 1 1 1 1')
sfr (key=UEP4 addr=0xf6e size=1 access='u u u rw rw rw rw rw')
    reset (por='---00000' mclr='---00000')
    bit (names='- - - EPHSHK EPCONDIS EPOUTEN EPINEN EPSTALL' width='1 1 1 1 1 1 1 1')
sfr (key=UEP5 addr=0xf6f size=1 access='u u u rw rw rw rw rw')
    reset (por='---00000' mclr='---00000')
    bit (names='- - - EPHSHK EPCONDIS EPOUTEN EPINEN EPSTALL' width='1 1 1 1 1 1 1 1')
sfr (key=UEP6 addr=0xf70 size=1 access='u u u rw rw rw rw rw')
    reset (por='---00000' mclr='---00000')
    bit (names='- - - EPHSHK EPCONDIS EPOUTEN EPINEN EPSTALL' width='1 1 1 1 1 1 1 1')
sfr (key=UEP7 addr=0xf71 size=1 access='u u u rw rw rw rw rw')
    reset (por='---00000' mclr='---00000')
    bit (names='- - - EPHSHK EPCONDIS EPOUTEN EPINEN EPSTALL' width='1 1 1 1 1 1 1 1')
sfr (key=UEP8 addr=0xf72 size=1 access='u u u rw rw rw rw rw')
    reset (por='---00000' mclr='---00000')
    bit (names='- - - EPHSHK EPCONDIS EPOUTEN EPINEN EPSTALL' width='1 1 1 1 1 1 1 1')
sfr (key=UEP9 addr=0xf73 size=1 access='u u u rw rw rw rw rw')
    reset (por='---00000' mclr='---00000')
    bit (names='- - - EPHSHK EPCONDIS EPOUTEN EPINEN EPSTALL' width='1 1 1 1 1 1 1 1')
sfr (key=UEP10 addr=0xf74 size=1 access='u u u rw rw rw rw rw')
    reset (por='---00000' mclr='---00000')
    bit (names='- - - EPHSHK EPCONDIS EPOUTEN EPINEN EPSTALL' width='1 1 1 1 1 1 1 1')
sfr (key=UEP11 addr=0xf75 size=1 access='u u u rw rw rw rw rw')
    reset (por='---00000' mclr='---00000')
    bit (names='- - - EPHSHK EPCONDIS EPOUTEN EPINEN EPSTALL' width='1 1 1 1 1 1 1 1')
sfr (key=UEP12 addr=0xf76 size=1 access='u u u rw rw rw rw rw')
    reset (por='---00000' mclr='---00000')
    bit (names='- - - EPHSHK EPCONDIS EPOUTEN EPINEN EPSTALL' width='1 1 1 1 1 1 1 1')
sfr (key=UEP13 addr=0xf77 size=1 access='u u u rw rw rw rw rw')
    reset (por='---00000' mclr='---00000')
    bit (names='- - - EPHSHK EPCONDIS EPOUTEN EPINEN EPSTALL' width='1 1 1 1 1 1 1 1')
sfr (key=UEP14 addr=0xf78 size=1 access='u u u rw rw rw rw rw')
    reset (por='---00000' mclr='---00000')
    bit (names='- - - EPHSHK EPCONDIS EPOUTEN EPINEN EPSTALL' width='1 1 1 1 1 1 1 1')
sfr (key=UEP15 addr=0xf79 size=1 access='u u u rw rw rw rw rw')
    reset (por='---00000' mclr='---00000')
    bit (names='- - - EPHSHK EPCONDIS EPOUTEN EPINEN EPSTALL' width='1 1 1 1 1 1 1 1')
sfr (key=SLRCON addr=0xf7a size=1 access='u u u rw rw rw rw rw')
    reset (por='---11111' mclr='---11111')
    bit (names='- - - SLRE SLRD SLRC SLRB SLRA' width='1 1 1 1 1 1 1 1')
sfr (key=VREFCON2 addr=0xf7b size=1 access='u u u rw rw rw rw rw')
    reset (por='---00000' mclr='---00000')
    bit (names='- - - DACR' width='1 1 1 5')
sfr (key=VREFCON1 addr=0xf7c size=1 access='rw rw rw u rw rw u rw')
    reset (por='000-00-0' mclr='000-00-0')
    bit (names='DACEN DACLPS DACOE - DACPSS - DACNSS' width='1 1 1 1 2 1 1')
sfr (key=VREFCON0 addr=0xf7d size=1 access='rw r rw rw rw rw u u')
    reset (por='000100--' mclr='000100--')
    bit (names='FVREN FVRST FVRS TSEN TSRNG - -' width='1 1 2 1 1 1 1')
sfr (key=PMD0 addr=0xf7e size=1 access='u rw rw rw u rw rw rw')
    reset (por='-000-000' mclr='-000-000')
    bit (names='- UARTMD USBMD ACTMD - TMR3MD TMR2MD TMR1MD' width='1 1 1 1 1 1 1 1')
sfr (key=PMD1 addr=0xf7f size=1 access='u rw rw rw rw rw rw rw')
    reset (por='-0000000' mclr='-0000000')
    bit (names='- MSSPMD CTMUMD CMP2MD CMP1MD ADCMD CCP2MD CCP1MD' width='1 1 1 1 1 1 1 1')
    stimulus (scl=rwb pcfiles=rw regfiles=w)
sfr (key=PORTA addr=0xf80 size=1 access='rw rw rw rw rw rw rw rw')
    reset (por='xxxxxxxx' mclr='uuuuuuuu')
    bit (names='RA7 RA6 RA5 RA4 RA3 RA2 RA1 RA0' width='1 1 1 1 1 1 1 1')
    bit (tag=scl names='RA' width='8')
    stimulus (scl=rwb pcfiles=rw regfiles=rw)
sfr (key=PORTB addr=0xf81 size=1 access='rw rw rw rw rw rw rw rw')
    reset (por='xxxxxxxx' mclr='uuuuuuuu')
    bit (names='RB7 RB6 RB5 RB4 RB3 RB2 RB1 RB0' width='1 1 1 1 1 1 1 1')
    bit (tag=scl names='RB' width='8')
    stimulus (scl=rwb pcfiles=rw regfiles=rw)
sfr (key=PORTC addr=0xf82 size=1 access='rw rw rw rw u rw rw rw')
    reset (por='xxxx-xxx' mclr='uuuu-uuu')
    bit (names='RC7 RC6 RC5 RC4 - RC2 RC1 RC0' width='1 1 1 1 1 1 1 1')
    bit (tag=scl names='RC' width='8')
    stimulus (scl=rwb pcfiles=rw regfiles=rw)
sfr (key=PORTD addr=0xf83 size=1 access='rw rw rw rw rw rw rw rw')
    reset (por='xxxxxxxx' mclr='uuuuuuuu')
    bit (names='RD7 RD6 RD5 RD4 RD3 RD2 RD1 RD0' width='1 1 1 1 1 1 1 1')
    bit (tag=scl names='RD' width='8')
    stimulus (scl=rwb pcfiles=rw regfiles=rw)
sfr (key=PORTE addr=0xf84 size=1 access='u u u u r rw rw rw')
    reset (por='----xxxx' mclr='----uuuu')
    bit (names='- - - - RE3 RE2 RE1 RE0' width='1 1 1 1 1 1 1 1')
    bit (tag=scl names='RE' width='8')
    stimulus (scl=rwb pcfiles=rw regfiles=rw)
sfr (key=WPUB addr=0xf85 size=1 access='rw rw rw rw rw rw rw rw')
    reset (por='11111111' mclr='11111111')
    bit (names='WPUB7 WPUB6 WPUB5 WPUB4 WPUB3 WPUB2 WPUB1 WPUB0' width='1 1 1 1 1 1 1 1')
    bit (tag=scl names='WPUB' width='8')
sfr (key=IOCB addr=0xf86 size=1 access='rw rw rw rw u u u u')
    reset (por='0000----' mclr='0000----')
    bit (names='IOCB7 IOCB6 IOCB5 IOCB4 - - - -' width='1 1 1 1 1 1 1 1')
sfr (key=IOCC addr=0xf87 size=1 access='rw rw rw rw u rw rw rw')
    reset (por='0000-000' mclr='0000-000')
    bit (names='IOCC7 IOCC6 IOCC5 IOCC4 - IOCC2 IOCC1 IOCC0' width='1 1 1 1 1 1 1 1')
sfr (key=CTMUICON addr=0xf88 size=1 access='rw rw rw rw rw rw rw rw')
    reset (por='00000000' mclr='00000000')
    bit (names='ITRIM IRNG' width='6 2')
sfr (key=LATA addr=0xf89 size=1 access='rw rw rw rw rw rw rw rw')
    reset (por='xxxxxxxx' mclr='xuuuuuuu')
    bit (names='LATA7 LATA6 LATA5 LATA4 LATA3 LATA2 LATA1 LATA0' width='1 1 1 1 1 1 1 1')
    bit (tag=scl names='LATA' width='8')
    stimulus (scl=rwb regfiles=w)
sfr (key=LATB addr=0xf8a size=1 access='rw rw rw rw rw rw rw rw')
    reset (por='xxxxxxxx' mclr='uuuuuuuu')
    bit (names='LATB7 LATB6 LATB5 LATB4 LATB3 LATB2 LATB1 LATB0' width='1 1 1 1 1 1 1 1')
    bit (tag=scl names='LATB' width='8')
    stimulus (scl=rwb regfiles=w)
sfr (key=LATC addr=0xf8b size=1 access='rw rw rw rw u rw rw rw')
    reset (por='xxxx-xxx' mclr='uuuu-uuu')
    bit (names='LATC7 LATC6 LATC5 LATC4 - LATC2 LATC1 LATC0' width='1 1 1 1 1 1 1 1')
    bit (tag=scl names='LATC' width='8')
    stimulus (scl=rwb regfiles=w)
sfr (key=LATD addr=0xf8c size=1 access='rw rw rw rw rw rw rw rw')
    reset (por='xxxxxxxx' mclr='uuuuuuuu')
    bit (names='LATD7 LATD6 LATD5 LATD4 LATD3 LATD2 LATD1 LATD0' width='1 1 1 1 1 1 1 1')
    bit (tag=scl names='LATD' width='8')
    stimulus (scl=rwb regfiles=w)
sfr (key=LATE addr=0xf8d size=1 access='u u u u u rw rw rw')
    reset (por='-----xxx' mclr='-----uuu')
    bit (names='- - - - - LATE2 LATE1 LATE0' width='1 1 1 1 1 1 1 1')
    bit (tag=scl names='LATE' width='8')
    stimulus (scl=rwb regfiles=w)
sfr (key=CTMUCONL addr=0xf8e size=1 access='rw rw rw rw rw rw rw rw')
    reset (por='000000xx' mclr='000000xx')
    bit (names='EDG2POL EDG2SEL EDG1POL EDG1SEL EDG2STAT EDG1STAT' width='1 2 1 2 1 1')
    stimulus (scl=rwb pcfiles=rw regfiles=w)
sfr (key=CTMUCONH addr=0xf8f size=1 access='rw u rw rw rw rw rw rw')
    reset (por='0-000000' mclr='0-000000')
    bit (names='CTMUEN - CTMUSIDL TGEN EDGEN EDGSEQEN IDISSEN CTTRIG' width='1 1 1 1 1 1 1 1')
    stimulus (scl=rwb pcfiles=rw regfiles=w)
sfr (key=CCPR2 addr=0xf90 size=2 flags=j)
    bit (names='CCPR1' width='16')
sfr (key=CCPR2L addr=0xf90 size=1 access='rw rw rw rw rw rw rw rw')
    reset (por='xxxxxxxx' mclr='uuuuuuuu')
    bit (names='CCPR2L' width='8')
    stimulus (scl=rwb regfiles=w type=int)
sfr (key=CCPR2H addr=0xf91 size=1 access='rw rw rw rw rw rw rw rw')
    reset (por='xxxxxxxx' mclr='uuuuuuuu')
    bit (names='CCPR2H' width='8')
    stimulus (scl=rwb regfiles=w type=int)
sfr (key=TRISA addr=0xf92 size=1 access='rw rw rw rw rw rw rw rw')
    reset (por='11111111' mclr='11111111')
    bit (names='TRISA7 TRISA6 TRISA5 TRISA4 TRISA3 TRISA2 TRISA1 TRISA0' width='1 1 1 1 1 1 1 1')
    bit (tag=scl names='TRISA' width='8')
    stimulus (scl=rwb regfiles=w)
sfr (key=TRISB addr=0xf93 size=1 access='rw rw rw rw rw rw rw rw')
    reset (por='11111111' mclr='11111111')
    bit (names='TRISB7 TRISB6 TRISB5 TRISB4 TRISB3 TRISB2 TRISB1 TRISB0' width='1 1 1 1 1 1 1 1')
    bit (tag=scl names='TRISB' width='8')
    stimulus (scl=rwb regfiles=w)
sfr (key=TRISC addr=0xf94 size=1 access='rw rw rw rw u rw rw rw')
    reset (por='1111-111' mclr='1111-111')
    bit (names='TRISC7 TRISC6 TRISC5 TRISC4 - TRISC2 TRISC1 TRISC0' width='1 1 1 1 1 1 1 1')
    bit (tag=scl names='TRISC' width='8')
    stimulus (scl=rwb regfiles=w)
sfr (key=TRISD addr=0xf95 size=1 access='rw rw rw rw rw rw rw rw')
    reset (por='11111111' mclr='11111111')
    bit (names='TRISD7 TRISD6 TRISD5 TRISD4 TRISD3 TRISD2 TRISD1 TRISD0' width='1 1 1 1 1 1 1 1')
    bit (tag=scl names='TRISD' width='8')
    stimulus (scl=rwb regfiles=w)
sfr (key=TRISE addr=0xf96 size=1 access='rw u u u u rw rw rw')
    reset (por='1----111' mclr='1----111')
    bit (names='WPUE3 - - - - TRISE2 TRISE1 TRISE0' width='1 1 1 1 1 1 1 1')
    bit (tag=scl names='TRISE' width='8')
    stimulus (scl=rwb regfiles=w)
sfr (key=CCP2CON addr=0xf97 size=1 access='u u rw rw rw rw rw rw')
    reset (por='--000000' mclr='--000000')
    bit (names='- - DC2B CCP2M' width='1 1 2 4')
    stimulus (scl=rwb regfiles=w)
sfr (key=CM1CON0 addr=0xf98 size=1 access='rw r rw rw rw rw rw rw')
    reset (por='00001000' mclr='00001000')
    bit (names='C1ON C1OUT C1OE C1POL C1SP C1R C1CH' width='1 1 1 1 1 1 2')
sfr (key=CM2CON0 addr=0xf99 size=1 access='rw r rw rw rw rw rw rw')
    reset (por='00001000' mclr='00001000')
    bit (names='C2ON C2OUT C2OE C2POL C2SP C2R C2CH' width='1 1 1 1 1 1 2')
sfr (key=CM2CON1 addr=0xf9a size=1 access='r r rw rw rw rw rw rw')
    reset (por='00000000' mclr='00000000')
    bit (names='MC1OUT MC2OUT C1RSEL C2RSEL C1HYS C2HYS C1SYNC C2SYNC' width='1 1 1 1 1 1 1 1')
    stimulus (scl=rwb regfiles=w)
sfr (key=OSCTUNE addr=0xf9b size=1 access='rw rw rw rw rw rw rw rw')
    reset (por='00000000' mclr='0uuuuuuu')
    bit (names='SPLLMULT TUN' width='1 7')
    stimulus (scl=rwb pcfiles=rw regfiles=w)
sfr (key=HLVDCON addr=0xf9c size=1 access='rw r r rw rw rw rw rw')
    reset (por='00000000' mclr='00000000')
    bit (names='VDIRMAG BGVST IRVST HLVDEN HLVDL' width='1 1 1 1 4')
    stimulus (scl=rwb regfiles=w)
sfr (key=PIE1 addr=0xf9d size=1 access='rw rw rw rw rw rw rw rw')
    reset (por='00000000' mclr='00000000')
    bit (names='ACTIE ADIE RCIE TXIE SSPIE CCP1IE TMR2IE TMR1IE' width='1 1 1 1 1 1 1 1')
    stimulus (scl=rwb pcfiles=rw regfiles=w)
sfr (key=PIR1 addr=0xf9e size=1 access='rw rw r r rw rw rw rw')
    reset (por='00000000' mclr='00000000')
    bit (names='ACTIF ADIF RCIF TXIF SSPIF CCP1IF TMR2IF TMR1IF' width='1 1 1 1 1 1 1 1')
    stimulus (scl=rwb pcfiles=rw regfiles=w)
sfr (key=IPR1 addr=0xf9f size=1 access='rw rw rw rw rw rw rw rw')
    reset (por='11111111' mclr='11111111')
    bit (names='ACTIP ADIP RCIP TXIP SSPIP CCP1IP TMR2IP TMR1IP' width='1 1 1 1 1 1 1 1')
    stimulus (scl=rwb pcfiles=rw regfiles=w)
sfr (key=PIE2 addr=0xfa0 size=1 access='rw rw rw rw rw rw rw rw')
    reset (por='00000000' mclr='00000000')
    bit (names='OSCFIE C1IE C2IE EEIE BCLIE HLVDIE TMR3IE CCP2IE' width='1 1 1 1 1 1 1 1')
    stimulus (scl=rwb pcfiles=rw regfiles=w)
sfr (key=PIR2 addr=0xfa1 size=1 access='rw rw rw rw rw rw rw rw')
    reset (por='00000000' mclr='00000000')
    bit (names='OSCFIF C1IF C2IF EEIF BCLIF HLVDIF TMR3IF CCP2IF' width='1 1 1 1 1 1 1 1')
    stimulus (scl=rwb pcfiles=rw regfiles=w)
sfr (key=IPR2 addr=0xfa2 size=1 access='rw rw rw rw rw rw rw rw')
    reset (por='11111111' mclr='11111111')
    bit (names='OSCFIP C1IP C2IP EEIP BCLIP HLVDIP TMR3IP CCP2IP' width='1 1 1 1 1 1 1 1')
    stimulus (scl=rwb pcfiles=rw regfiles=w)
sfr (key=PIE3 addr=0xfa3 size=1 access='u u u u rw rw rw rw')
    reset (por='----0000' mclr='----0000')
    bit (names='- - - - CTMUIE USBIE TMR3GIE TMR1GIE' width='1 1 1 1 1 1 1 1')
sfr (key=PIR3 addr=0xfa4 size=1 access='u u u u rw rw rw rw')
    reset (por='----0000' mclr='----0000')
    bit (names='- - - - CTMUIF USBIF TMR3GIF TMR1GIF' width='1 1 1 1 1 1 1 1')
sfr (key=IPR3 addr=0xfa5 size=1 access='u u u u rw rw rw rw')
    reset (por='----1111' mclr='----1111')
    bit (names='- - - - CTMUIP USBIP TMR3GIP TMR1GIP' width='1 1 1 1 1 1 1 1')
sfr (key=EECON1 addr=0xfa6 size=1 access='rw rw u rw rw rw rs rs')
    reset (por='xx-0x000' mclr='uu-0u000')
    bit (names='EEPGD CFGS - FREE WRERR WREN WR RD' width='1 1 1 1 1 1 1 1')
sfr (key=EECON2 addr=0xfa7 size=1 access='w w w w w w w w')
    reset (por='--------' mclr='--------')
    bit (names='EECON2' width='8')
sfr (key=EEDATA addr=0xfa8 size=1 access='rw rw rw rw rw rw rw rw')
    reset (por='00000000' mclr='00000000')
    bit (names='EEDATA' width='8')
    stimulus (scl=rwb pcfiles=rw regfiles=rw)
sfr (key=EEADR addr=0xfa9 size=1 access='rw rw rw rw rw rw rw rw')
    reset (por='00000000' mclr='00000000')
    bit (names='EEADR' width='8')
    stimulus (scl=rwb pcfiles=rw regfiles=w)
UnusedRegs (0xfaa-0xfaa)
sfr (key=RCSTA1 addr=0xfab size=1 access='rw rw rw rw rw r r r')
    reset (por='0000000x' mclr='0000000x')
    bit (names='SPEN RX9 SREN CREN ADDEN FERR OERR RX9D' width='1 1 1 1 1 1 1 1')
sfr (key=TXSTA1 addr=0xfac size=1 access='rw rw rw rw rw rw r rw')
    reset (por='00000010' mclr='00000010')
    bit (names='CSRC TX9 TXEN SYNC SENDB BRGH TRMT TX9D' width='1 1 1 1 1 1 1 1')
sfr (key=TXREG1 addr=0xfad size=1 access='w w w w w w w w')
    reset (por='00000000' mclr='00000000')
    bit (names='TXREG1' width='8')
sfr (key=RCREG1 addr=0xfae size=1 access='r r r r r r r r')
    reset (por='00000000' mclr='00000000')
    bit (names='RCREG1' width='8')
sfr (key=SPBRG1 addr=0xfaf size=1 access='rw rw rw rw rw rw rw rw')
    reset (por='00000000' mclr='00000000')
    bit (names='SPBRG1' width='8')
sfr (key=SPBRGH1 addr=0xfb0 size=1 access='rw rw rw rw rw rw rw rw')
    reset (por='00000000' mclr='00000000')
    bit (names='SPBRGH1' width='8')
sfr (key=T3CON addr=0xfb1 size=1 access='rw rw rw rw rw rw rw rw')
    reset (por='00000000' mclr='uuuuuuuu')
    bit (names='TMR3CS T3CKPS SOSCEN nT3SYNC RD16 TMR3ON' width='2 2 1 1 1 1')
sfr (key=TMR3 addr=0xfb2 size=2 flags=j)
sfr (key=TMR3L addr=0xfb2 size=1 access='rw rw rw rw rw rw rw rw')
    reset (por='xxxxxxxx' mclr='uuuuuuuu')
    bit (names='TMR3L' width='8')
sfr (key=TMR3H addr=0xfb3 size=1 access='rw rw rw rw rw rw rw rw')
    reset (por='xxxxxxxx' mclr='uuuuuuuu')
    bit (names='TMR3H' width='8')
sfr (key=T3GCON addr=0xfb4 size=1 access='rw rw rw rw rw r rw rw')
    reset (por='00000x00' mclr='uuuuuxuu')
    bit (names='TMR3GE T3GPOL T3GTM T3GSPM T3GGO_nT3DONE T3GVAL T3GSS' width='1 1 1 1 1 1 2')
sfr (key=ACTCON addr=0xfb5 size=1 access='rw rw u rw r u r u')
    reset (por='00-00-0-' mclr='00-00-0-')
    bit (names='ACTEN ACTUD - ACTSRC ACTLOCK - ACTORS -' width='1 1 1 1 1 1 1 1')
sfr (key=ECCP1AS addr=0xfb6 size=1 access='rw rw rw rw rw rw rw rw')
    reset (por='00000000' mclr='00000000')
    bit (names='ECCP1ASE ECCP1AS PSS1AC PSS1BD' width='1 3 2 2')
    stimulus (scl=rwb regfiles=w)
sfr (key=PWM1CON addr=0xfb7 size=1 access='rw rw rw rw rw rw rw rw')
    reset (por='00000000' mclr='00000000')
    bit (names='P1RSEN P1DC' width='1 7')
sfr (key=BAUDCON1 addr=0xfb8 size=1 access='rw r rw rw rw u rw rw')
    reset (por='01000-00' mclr='01000-00')
    bit (names='ABDOVF RCIDL RXDTP TXCKP BRG16 - WUE ABDEN' width='1 1 1 1 1 1 1 1')
sfr (key=PSTR1CON addr=0xfb9 size=1 access='u u u rw rw rw rw rw')
    reset (por='---00001' mclr='---00001')
    bit (names='- - - STRSYNC STRD STRC STRB STRA' width='1 1 1 1 1 1 1 1')
    stimulus (scl=rwb regfiles=w)
sfr (key=T2CON addr=0xfba size=1 access='u rw rw rw rw rw rw rw')
    reset (por='-0000000' mclr='-0000000')
    bit (names='- T2OUTPS TMR2ON T2CKPS' width='1 4 1 2')
sfr (key=PR2 addr=0xfbb size=1 access='rw rw rw rw rw rw rw rw')
    reset (por='11111111' mclr='11111111')
    bit (names='PR2' width='8')
sfr (key=TMR2 addr=0xfbc size=1 access='rw rw rw rw rw rw rw rw')
    reset (por='00000000' mclr='00000000')
    bit (names='TMR2' width='8')
sfr (key=CCP1CON addr=0xfbd size=1 access='rw rw rw rw rw rw rw rw')
    reset (por='00000000' mclr='00000000')
    bit (names='P1M DC1B CCP1M' width='2 2 4')
    stimulus (scl=rwb regfiles=w)
sfr (key=CCPR1 addr=0xfbe size=2 flags=j)
    bit (names='CCPR1' width='16')
sfr (key=CCPR1L addr=0xfbe size=1 access='rw rw rw rw rw rw rw rw')
    reset (por='xxxxxxxx' mclr='uuuuuuuu')
    bit (names='CCPR1L' width='8')
    stimulus (scl=rwb regfiles=w type=int)
sfr (key=CCPR1H addr=0xfbf size=1 access='rw rw rw rw rw rw rw rw')
    reset (por='xxxxxxxx' mclr='uuuuuuuu')
    bit (names='CCPR1H' width='8')
    stimulus (scl=rwb regfiles=w type=int)
sfr (key=ADCON2 addr=0xfc0 size=1 access='rw u rw rw rw rw rw rw')
    reset (por='0-000000' mclr='0-000000')
    bit (names='ADFM - ACQT ADCS' width='1 1 3 3')
    stimulus (scl=rwb regfiles=w)
sfr (key=ADCON1 addr=0xfc1 size=1 access='rw u u u rw rw rw rw')
    reset (por='0---0000' mclr='0---0000')
    bit (names='TRIGSEL - - - PVCFG NVCFG' width='1 1 1 1 2 2')
    stimulus (scl=rwb regfiles=w)
sfr (key=ADCON0 addr=0xfc2 size=1 access='u rw rw rw rw rw rw rw')
    reset (por='-0000000' mclr='-00000u0')
    bit (names='- CHS GO/nDONE ADON' width='1 5 1 1')
    bit (tag=scl names='- CHS4 CHS3 CHS2 CHS1 CHS0 GO_DONE -' width='1 1 1 1 1 1 1 1')
    stimulus (scl=rwb regfiles=w)
sfr (key=ADRESL addr=0xfc3 size=1 access='rw rw rw rw rw rw rw rw')
    reset (por='xxxxxxxx' mclr='uuuuuuuu')
    bit (names='ADRESL' width='8')
    stimulus (scl=rwb regfiles=r type=int)
sfr (key=ADRESH addr=0xfc4 size=1 access='rw rw rw rw rw rw rw rw')
    reset (por='xxxxxxxx' mclr='uuuuuuuu')
    bit (names='ADRESH' width='8')
    stimulus (scl=rwb regfiles=w type=int)
sfr (key=SSP1CON2 addr=0xfc5 size=1 access='rw r rw rw rw rw rw rw')
    reset (por='00000000' mclr='00000000')
    bit (names='GCEN ACKSTAT ACKDT ACKEN RCEN PEN RSEN SEN' width='1 1 1 1 1 1 1 1')
sfr (key=SSP1CON1 addr=0xfc6 size=1 access='rw rc rw rw rw rw rw rw')
    reset (por='00000000' mclr='00000000')
    bit (names='WCOL SSPOV SSPEN CKP SSPM' width='1 1 1 1 4')
sfr (key=SSP1STAT addr=0xfc7 size=1 access='rw rw rw rw rw rw rw rw')
    reset (por='00000000' mclr='00000000')
    bit (names='SMP CKE D_nA P S R_nW UA BF' width='1 1 1 1 1 1 1 1')
sfr (key=SSP1ADD addr=0xfc8 size=1 access='rw rw rw rw rw rw rw rw')
    reset (por='00000000' mclr='00000000')
    bit (names='SSP1ADD' width='8')
sfr (key=SSP1BUF addr=0xfc9 size=1 access='rw rw rw rw rw rw rw rw')
    reset (por='xxxxxxxx' mclr='uuuuuuuu')
    bit (names='SSP1BUF' width='8')
sfr (key=SSP1MSK addr=0xfca size=1 access='rw rw rw rw rw rw rw rw')
    reset (por='11111111' mclr='11111111')
    bit (names='SSP1MSK' width='8')
sfr (key=SSP1CON3 addr=0xfcb size=1 access='r rw rw rw rw rw rw rw')
    reset (por='00000000' mclr='00000000')
    bit (names='ACKTIM PCIE SCIE BOEN SDAHT SBCDE AHEN DHEN' width='1 1 1 1 1 1 1 1')
sfr (key=T1GCON addr=0xfcc size=1 access='rw rw rw rw rw r rw rw')
    reset (por='00000x00' mclr='uuuuuxuu')
    bit (names='TMR1GE T1GPOL T1GTM T1GSPM T1GGO_nT1DONE T1GVAL T1GSS' width='1 1 1 1 1 1 2')
sfr (key=T1CON addr=0xfcd size=1 access='rw rw rw rw rw rw rw rw')
    reset (por='00000000' mclr='uuuuuuuu')
    bit (names='TMR1CS T1CKPS SOSCEN nT1SYNC RD16 TMR1ON' width='2 2 1 1 1 1')
sfr (key=TMR1 addr=0xfce size=2 flags=j)
sfr (key=TMR1L addr=0xfce size=1 access='rw rw rw rw rw rw rw rw')
    reset (por='xxxxxxxx' mclr='uuuuuuuu')
    bit (names='TMR1L' width='8')
sfr (key=TMR1H addr=0xfcf size=1 access='rw rw rw rw rw rw rw rw')
    reset (por='xxxxxxxx' mclr='uuuuuuuu')
    bit (names='TMR1H' width='8')
sfr (key=RCON addr=0xfd0 size=1 access='rw rw u rw rw rw rw rw')
    reset (por='01-11100' mclr='01-qqquu')
    bit (names='IPEN SBOREN - nRI nTO nPD nPOR nBOR' width='1 1 1 1 1 1 1 1')
    stimulus (scl=r pcfiles=rw regfiles=w)
sfr (key=WDTCON addr=0xfd1 size=1 access='u u u u u u u rw')
    reset (por='-------0' mclr='-------0')
    bit (names='- - - - - - - SWDTEN' width='1 1 1 1 1 1 1 1')
    stimulus (scl=rwb pcfiles=rw regfiles=w)
sfr (key=OSCCON2 addr=0xfd2 size=1 access='r r rw rw rw rw r r')
    reset (por='00000100' mclr='00000100')
    bit (names='PLLRDY SOSCRUN INTSRC PLLEN SOSCGO PRISD HFIOFR LFIOFS' width='1 1 1 1 1 1 1 1')
sfr (key=OSCCON addr=0xfd3 size=1 access='rw rw rw rw r r rw rw')
    reset (por='0011q000' mclr='0011q000')
    bit (names='IDLEN IRCF OSTS HFIOFS SCS' width='1 3 1 1 2')
    stimulus (scl=rwb pcfiles=rw regfiles=w)
UnusedRegs (0xfd4-0xfd4)
sfr (key=T0CON addr=0xfd5 size=1 access='rw rw rw rw rw rw rw rw')
    reset (por='11111111' mclr='11111111')
    bit (names='TMR0ON T08BIT T0CS T0SE PSA T0PS' width='1 1 1 1 1 3')
sfr (key=TMR0 addr=0xfd6 size=2 flags=j)
sfr (key=TMR0L addr=0xfd6 size=1 access='rw rw rw rw rw rw rw rw')
    reset (por='xxxxxxxx' mclr='uuuuuuuu')
    bit (names='TMR0L' width='8')
sfr (key=TMR0H addr=0xfd7 size=1 access='rw rw rw rw rw rw rw rw')
    reset (por='00000000' mclr='00000000')
    bit (names='TMR0H' width='8')
sfr (key=STATUS addr=0xfd8 size=1 access='u u u rw rw rw rw rw')
    reset (por='---xxxxx' mclr='---uuuuu')
    bit (names='- - - N OV Z DC C' width='1 1 1 1 1 1 1 1')
sfr (key=FSR2 addr=0xfd9 size=2 flags=j)
    bit (names='- - - - FSR2' width='1 1 1 1 12')
sfr (key=FSR2L addr=0xfd9 size=1 access='rw rw rw rw rw rw rw rw')
    reset (por='xxxxxxxx' mclr='uuuuuuuu')
    bit (names='FSR2L' width='8')
    stimulus (scl=rwb pcfiles=rw regfiles=w)
sfr (key=FSR2H addr=0xfda size=1 access='u u u u rw rw rw rw')
    reset (por='----0000' mclr='----0000')
    bit (names='- - - - FSR2H' width='1 1 1 1 4')
    stimulus (scl=rwb pcfiles=rw regfiles=w)
sfr (key=PLUSW2 addr=0xfdb size=1 flags=i access='u u u u u u u u')
    reset (por='--------' mclr='--------')
    bit (names='PLUSW2' width='8')
sfr (key=PREINC2 addr=0xfdc size=1 flags=i access='u u u u u u u u')
    reset (por='--------' mclr='--------')
    bit (names='PREINC2' width='8')
sfr (key=POSTDEC2 addr=0xfdd size=1 flags=i access='u u u u u u u u')
    reset (por='--------' mclr='--------')
    bit (names='POSTDEC2' width='8')
sfr (key=POSTINC2 addr=0xfde size=1 flags=i access='u u u u u u u u')
    reset (por='--------' mclr='--------')
    bit (names='POSTINC2' width='8')
sfr (key=INDF2 addr=0xfdf size=1 flags=i access='u u u u u u u u')
    reset (por='--------' mclr='--------')
    bit (names='INDF2' width='8')
sfr (key=BSR addr=0xfe0 size=1 access='u u u u rw rw rw rw')
    reset (por='----0000' mclr='----0000')
    bit (names='- - - - BSR' width='1 1 1 1 4')
    stimulus (scl=rwb pcfiles=rw regfiles=w)
sfr (key=FSR1 addr=0xfe1 size=2 flags=j)
    bit (names='- - - - FSR1' width='1 1 1 1 12')
sfr (key=FSR1L addr=0xfe1 size=1 access='rw rw rw rw rw rw rw rw')
    reset (por='xxxxxxxx' mclr='uuuuuuuu')
    bit (names='FSR1L' width='8')
    stimulus (scl=rwb pcfiles=rw regfiles=w)
sfr (key=FSR1H addr=0xfe2 size=1 access='u u u u rw rw rw rw')
    reset (por='----0000' mclr='----uuuu')
    bit (names='- - - - FSR1H' width='1 1 1 1 4')
    stimulus (scl=rwb pcfiles=rw regfiles=w)
sfr (key=PLUSW1 addr=0xfe3 size=1 flags=i access='u u u u u u u u')
    reset (por='--------' mclr='--------')
    bit (names='PLUSW1' width='8')
sfr (key=PREINC1 addr=0xfe4 size=1 flags=i access='u u u u u u u u')
    reset (por='--------' mclr='--------')
    bit (names='PREINC1' width='8')
sfr (key=POSTDEC1 addr=0xfe5 size=1 flags=i access='u u u u u u u u')
    reset (por='--------' mclr='--------')
    bit (names='POSTDEC1' width='8')
sfr (key=POSTINC1 addr=0xfe6 size=1 flags=i access='u u u u u u u u')
    reset (por='--------' mclr='--------')
    bit (names='POSTINC1' width='8')
sfr (key=INDF1 addr=0xfe7 size=1 flags=i access='u u u u u u u u')
    reset (por='--------' mclr='--------')
    bit (names='INDF1' width='8')
sfr (key=WREG addr=0xfe8 size=1 access='rw rw rw rw rw rw rw rw')
    reset (por='xxxxxxxx' mclr='uuuuuuuu')
    bit (names='WREG' width='8')
    stimulus (scl=rwb pcfiles=rw regfiles=w type=int)
sfr (key=FSR0 addr=0xfe9 size=2 flags=j)
    bit (names='- - - - FSR0' width='1 1 1 1 12')
sfr (key=FSR0L addr=0xfe9 size=1 access='rw rw rw rw rw rw rw rw')
    reset (por='xxxxxxxx' mclr='uuuuuuuu')
    bit (names='FSR0L' width='8')
    stimulus (scl=rwb pcfiles=rw regfiles=w)
sfr (key=FSR0H addr=0xfea size=1 access='u u u u rw rw rw rw')
    reset (por='----0000' mclr='----uuuu')
    bit (names='- - - - FSR0H' width='1 1 1 1 4')
    stimulus (scl=rwb pcfiles=rw regfiles=w)
sfr (key=PLUSW0 addr=0xfeb size=1 flags=i access='u u u u u u u u')
    reset (por='--------' mclr='--------')
    bit (names='PLUSW0' width='8')
sfr (key=PREINC0 addr=0xfec size=1 flags=i access='u u u u u u u u')
    reset (por='--------' mclr='--------')
    bit (names='PREINC0' width='8')
sfr (key=POSTDEC0 addr=0xfed size=1 flags=i access='u u u u u u u u')
    reset (por='--------' mclr='--------')
    bit (names='POSTDEC0' width='8')
sfr (key=POSTINC0 addr=0xfee size=1 flags=i access='u u u u u u u u')
    reset (por='--------' mclr='--------')
    bit (names='POSTINC0' width='8')
sfr (key=INDF0 addr=0xfef size=1 flags=i access='u u u u u u u u')
    reset (por='--------' mclr='--------')
    bit (names='INDF0' width='8')
sfr (key=INTCON3 addr=0xff0 size=1 access='rw rw u rw rw u rw rw')
    reset (por='11-00-00' mclr='11-00-00')
    bit (names='INT2IP INT1IP - INT2IE INT1IE - INT2IF INT1IF' width='1 1 1 1 1 1 1 1')
    stimulus (scl=rwb pcfiles=rw regfiles=w)
sfr (key=INTCON2 addr=0xff1 size=1 access='rw rw rw rw u rw u rw')
    reset (por='1111-1-1' mclr='1111-1-1')
    bit (names='nRBPU INTEDG0 INTEDG1 INTEDG2 - TMR0IP - IOCIP' width='1 1 1 1 1 1 1 1')
    stimulus (scl=rwb pcfiles=rw regfiles=w)
sfr (key=INTCON addr=0xff2 size=1 access='rw rw rw rw rw rw rw rw')
    reset (por='0000000x' mclr='0000000u')
    bit (names='GIE/GIEH PEIE/GIEL TMR0IE INT0IE IOCIE TMR0IF INT0IF IOCIF' width='1 1 1 1 1 1 1 1')
    # NOTE: When IPEN (bit 7) in the RCON register is 0 use the following bit names
    qbit (names='GIE PEIE - - - - - -' width='1 1 1 1 1 1 1 1')
    # NOTE: When IPEN (bit 7) in the RCON register is 1 use the following bit names
    qbit (names='GIEH GIEL - - - - - -' width='1 1 1 1 1 1 1 1')
    stimulus (scl=rwb pcfiles=rw regfiles=w)
sfr (key=PROD addr=0xff3 size=2 flags=j)
sfr (key=PRODL addr=0xff3 size=1 access='rw rw rw rw rw rw rw rw')
    reset (por='xxxxxxxx' mclr='uuuuuuuu')
    bit (names='PRODL' width='8')
sfr (key=PRODH addr=0xff4 size=1 access='rw rw rw rw rw rw rw rw')
    reset (por='xxxxxxxx' mclr='uuuuuuuu')
    bit (names='PRODH' width='8')
sfr (key=TABLAT addr=0xff5 size=1 access='rw rw rw rw rw rw rw rw')
    reset (por='00000000' mclr='00000000')
    bit (names='TABLAT' width='8')
sfr (key=TBLPTR addr=0xff6 size=3 flags=j)
sfr (key=TBLPTRL addr=0xff6 size=1 access='rw rw rw rw rw rw rw rw')
    reset (por='00000000' mclr='00000000')
    bit (names='TBLPTRL' width='8')
sfr (key=TBLPTRH addr=0xff7 size=1 access='rw rw rw rw rw rw rw rw')
    reset (por='00000000' mclr='00000000')
    bit (names='TBLPTRH' width='8')
sfr (key=TBLPTRU addr=0xff8 size=1 access='u u rw rw rw rw rw rw')
    reset (por='--000000' mclr='--000000')
    bit (names='- - ACSS TBLPTRU' width='1 1 1 5')
sfr (key=PCLAT addr=0xff9 size=3 flags=j)
sfr (key=PCL addr=0xff9 size=1 access='rw rw rw rw rw rw rw rw')
    reset (por='00000000' mclr='00000000')
    bit (names='PCL' width='8')
sfr (key=PCLATH addr=0xffa size=1 access='rw rw rw rw rw rw rw rw')
    reset (por='00000000' mclr='00000000')
    bit (names='PCH' width='8')
sfr (key=PCLATU addr=0xffb size=1 access='u u u rw rw rw rw rw')
    reset (por='---00000' mclr='---00000')
    bit (names='- - - PCU' width='1 1 1 5')
sfr (key=STKPTR addr=0xffc size=1 access='rc rc u rw rw rw rw rw')
    reset (por='00-00000' mclr='00-00000')
    bit (names='STKFUL STKUNF - STKPTR' width='1 1 1 5')
sfr (key=TOS addr=0xffd size=3 flags=j)
sfr (key=TOSL addr=0xffd size=1 access='rw rw rw rw rw rw rw rw')
    reset (por='00000000' mclr='00000000')
    bit (names='TOSL' width='8')
sfr (key=TOSH addr=0xffe size=1 access='rw rw rw rw rw rw rw rw')
    reset (por='00000000' mclr='00000000')
    bit (names='TOSH' width='8')
sfr (key=TOSU addr=0xfff size=1 access='u u u rw rw rw rw rw')
    reset (por='---00000' mclr='---00000')
    bit (names='- - - TOSU' width='1 1 1 5')

######################################################################
#
# Non Memory-Mapped Registers
#
# (Conditionally visible SFRs appear as NMMRs in the "Special Function
# Registers" section.)
#
######################################################################

HasNMMR=1
nmmr (key=TMR0_Internal addr=0xa size=2 access='r r r r r r r r r r r r r r r r')
    reset (por='xxxxxxxxxxxxxxxx' mclr='uuuuuuuuuuuuuuuu')
    bit (names='InternalTMR' width='16')
nmmr (key=TMR0_Prescale addr=0x12 size=1 access='rw rw rw rw rw rw rw rw')
    reset (por='xxxxxxxx' mclr='uuuuuuuu')
    bit (names='InternalPS' width='8')
nmmr (key=TMR1_Internal addr=0xc size=2 access='r r r r r r r r r r r r r r r r')
    reset (por='xxxxxxxxxxxxxxxx' mclr='uuuuuuuuuuuuuuuu')
    bit (names='InternalTMR' width='16')
nmmr (key=TMR1_Prescale addr=0x13 size=1 access='rw rw rw rw rw rw rw rw')
    reset (por='xxxxxxxx' mclr='uuuuuuuu')
    bit (names='InternalPS' width='8')
nmmr (key=TMR2_Prescale addr=0x14 size=1 access='rw rw rw rw rw rw rw rw')
    reset (por='xxxxxxxx' mclr='uuuuuuuu')
    bit (names='InternalPS' width='8')
nmmr (key=TMR3_Internal addr=0xe size=2 access='r r r r r r r r r r r r r r r r')
    reset (por='xxxxxxxxxxxxxxxx' mclr='uuuuuuuuuuuuuuuu')
    bit (names='InternalTMR' width='16')
nmmr (key=TMR3_Prescale addr=0x15 size=1 access='rw rw rw rw rw rw rw rw')
    reset (por='xxxxxxxx' mclr='uuuuuuuu')
    bit (names='InternalPS' width='8')
NMMRObjSize=7

######################################################################
#
# Configuration Registers
#
######################################################################

cfgbits (key=CONFIG1L addr=0x300000 unused=0x0)
    field (key=PLLSEL mask=0x1 desc="PLL Selection" init=0x0)
        setting (req=0x1 value=0x1 desc="3x clock multiplier")
        setting (req=0x1 value=0x0 desc="4x clock multiplier")
    field (key=CFGPLLEN mask=0x2 desc="PLL Enable Configuration bit" init=0x0)
        setting (req=0x2 value=0x2 desc="Enabled")
        setting (req=0x2 value=0x0 desc="Disabled")
    field (key=CPUDIV mask=0x18 desc="CPU System Clock Postscaler" init=0x0)
        setting (req=0x18 value=0x18 desc="CPU uses system clock divided by 6")
        setting (req=0x18 value=0x10 desc="CPU uses system clock divided by 3")
        setting (req=0x18 value=0x8 desc="CPU uses system clock divided by 2")
        setting (req=0x18 value=0x0 desc="CPU uses system clock (no divide)")
    field (key=LS48MHZ mask=0x20 desc="Low Speed USB mode with 48 MHz system clock" init=0x0)
        setting (req=0x20 value=0x20 desc="System clock at 48 MHz, USB clock divider is set to 8")
        setting (req=0x20 value=0x0 desc="System clock at 24 MHz, USB clock divider is set to 4")
cfgbits (key=CONFIG1H addr=0x300001 unused=0x0)
    field (key=FOSC mask=0xf desc="Oscillator Selection" init=0x5)
        setting (req=0xf value=0xd desc="EC oscillator, low power <4MHz")
        setting (req=0xf value=0xc desc="EC oscillator, low power <4MHz, clock output on OSC2")
        setting (req=0xf value=0xb desc="EC oscillator, medium power 4MHz to 16MHz")
        setting (req=0xf value=0xa desc="EC oscillator, medium power 4MHz to 16MHz, clock output on OSC2")
        setting (req=0xf value=0x5 desc="EC oscillator, high power 16MHz to 48MHz")
        setting (req=0xf value=0x4 desc="EC oscillator, high power 16MHz to 48MHz, clock output on OSC2")
        setting (req=0xf value=0x7 desc="External RC oscillator")
        setting (req=0xf value=0x6 desc="External RC oscillator, clock output on OSC2")
        setting (req=0xf value=0x8 desc="Internal oscillator")
        setting (req=0xf value=0x9 desc="Internal oscillator, clock output on OSC2")
        setting (req=0xf value=0x3 desc="HS oscillator, medium power 4MHz to 16MHz")
        setting (req=0xf value=0x2 desc="HS oscillator, high power 16MHz to 25MHz")
        setting (req=0xf value=0x1 desc="XT oscillator")
        setting (req=0xf value=0x0 desc="LP oscillator")
    field (key=PCLKEN mask=0x20 desc="Primary Oscillator Shutdown")
        setting (req=0x20 value=0x20 desc="Enabled")
        setting (req=0x20 value=0x0 desc="Disabled")
    field (key=FCMEN mask=0x40 desc="Fail-Safe Clock Monitor" init=0x0)
        setting (req=0x40 value=0x40 desc="Enabled")
        setting (req=0x40 value=0x0 desc="Disabled")
    field (key=IESO mask=0x80 desc="Internal/External Oscillator Switchover" init=0x0)
        setting (req=0x80 value=0x80 desc="Enabled")
        setting (req=0x80 value=0x0 desc="Disabled")
cfgbits (key=CONFIG2L addr=0x300002 unused=0x0)
    field (key=nPWRTEN mask=0x1 desc="Power-up Timer Enable")
        setting (req=0x1 value=0x1 desc="Disabled")
        setting (req=0x1 value=0x0 desc="Enabled")
    field (key=BOREN mask=0x6 desc="Brown-out Reset Enable")
        setting (req=0x6 value=0x6 desc="BOR enabled in hardware (SBOREN is ignored)")
        setting (req=0x6 value=0x4 desc="BOR enabled in hardware, disabled in Sleep mode (SBOREN is ignored)")
        setting (req=0x6 value=0x2 desc="Enabled")
        setting (req=0x6 value=0x0 desc="Disabled")
    field (key=BORV mask=0x18 desc="Brown-out Reset Voltage")
        setting (req=0x18 value=0x18 desc="BOR set to 1.9V nominal")
        setting (req=0x18 value=0x10 desc="BOR set to 2.2V nominal")
        setting (req=0x18 value=0x8 desc="BOR set to 2.5V nominal")
        setting (req=0x18 value=0x0 desc="BOR set to 2.85V nominal")
    field (key=nLPBOR mask=0x40 desc="Low-Power Brown-out Reset")
        setting (req=0x40 value=0x40 desc="Disabled")
        setting (req=0x40 value=0x0 desc="Enabled")
cfgbits (key=CONFIG2H addr=0x300003 unused=0x0)
    field (key=WDTEN mask=0x3 desc="Watchdog Timer Enable bits" min=4)
        setting (req=0x3 value=0x3 desc="Enabled")
        setting (req=0x3 value=0x2 desc="WDT controlled by firmware (SWDTEN enabled)")
        setting (req=0x3 value=0x1 desc="WDT enabled in hardware, disabled in Sleep mode (SWDTEN ignored)")
        setting (req=0x3 value=0x0 desc="Disabled")
    field (key=WDTPS mask=0x3c desc="Watchdog Timer Postscaler")
        setting (req=0x3c value=0x3c desc="1:32768")
        setting (req=0x3c value=0x38 desc="1:16384")
        setting (req=0x3c value=0x34 desc="1:8192")
        setting (req=0x3c value=0x30 desc="1:4096")
        setting (req=0x3c value=0x2c desc="1:2048")
        setting (req=0x3c value=0x28 desc="1:1024")
        setting (req=0x3c value=0x24 desc="1:512")
        setting (req=0x3c value=0x20 desc="1:256")
        setting (req=0x3c value=0x1c desc="1:128")
        setting (req=0x3c value=0x18 desc="1:64")
        setting (req=0x3c value=0x14 desc="1:32")
        setting (req=0x3c value=0x10 desc="1:16")
        setting (req=0x3c value=0xc desc="1:8")
        setting (req=0x3c value=0x8 desc="1:4")
        setting (req=0x3c value=0x4 desc="1:2")
        setting (req=0x3c value=0x0 desc="1:1")
cfgbits (key=CONFIG3H addr=0x300005 unused=0x0)
    field (key=CCP2MX mask=0x1 desc="CCP2 MUX bit")
        setting (req=0x1 value=0x1 desc="CCP2 input/output is multiplexed with RC1")
        setting (req=0x1 value=0x0 desc="CCP2 input/output is multiplexed with RB3")
    field (key=PBADEN mask=0x2 desc="PORTB A/D Enable bit")
        setting (req=0x2 value=0x2 desc="Enabled")
        setting (req=0x2 value=0x0 desc="Disabled")
    field (key=T3CMX mask=0x10 desc="Timer3 Clock Input MUX bit")
        setting (req=0x10 value=0x10 desc="T3CKI function is on RC0")
        setting (req=0x10 value=0x0 desc="T3CKI function is on RB5")
    field (key=SDOMX mask=0x40 desc="SDO Output MUX bit")
        setting (req=0x40 value=0x40 desc="SDO function is on RB3")
        setting (req=0x40 value=0x0 desc="SDO function is on RC7")
    field (key=MCLRE mask=0x80 desc="Master Clear Reset Pin Enable")
        setting (req=0x80 value=0x80 desc="Enabled")
        setting (req=0x80 value=0x0 desc="Disabled")
cfgbits (key=CONFIG4L addr=0x300006 unused=0x0)
    field (key=STVREN mask=0x1 desc="Stack Full/Underflow Reset")
        setting (req=0x1 value=0x1 desc="Enabled")
        setting (req=0x1 value=0x0 desc="Disabled")
    field (key=LVP mask=0x4 desc="Single-Supply ICSP Enable bit")
        setting (req=0x4 value=0x4 desc="Enabled")
        setting (req=0x4 value=0x0 desc="Disabled")
    field (key=ICPRT mask=0x20 desc="Dedicated In-Circuit Debug/Programming Port Enable" init=0x0)
        setting (req=0x20 value=0x20 desc="Enabled")
        setting (req=0x20 value=0x0 desc="Disabled")
    field (key=XINST mask=0x40 desc="Extended Instruction Set Enable bit" init=0x0)
        setting (req=0x40 value=0x40 desc="Enabled")
        setting (req=0x40 value=0x0 desc="Disabled")
    field (key=DEBUG mask=0x80 desc="Background Debugger Enable bit" flags=h)
        setting (req=0x80 value=0x80 desc="Disabled")
        setting (req=0x80 value=0x0 desc="Enabled")
cfgbits (key=CONFIG5L addr=0x300008 unused=0x0)
    field (key=CP0 mask=0x1 desc="Block 0 Code Protect")
        setting (req=0x1 value=0x1 desc="Disabled")
            checksum (type=0x0 protregion=0x0-0x0)
        setting (req=0x1 value=0x0 desc="Enabled")
            checksum (type=0x27 protregion=0x800-0x1fff)
    field (key=CP1 mask=0x2 desc="Block 1 Code Protect")
        setting (req=0x2 value=0x2 desc="Disabled")
            checksum (type=0x0 protregion=0x0-0x0)
        setting (req=0x2 value=0x0 desc="Enabled")
            checksum (type=0x27 protregion=0x2000-0x3fff)
    field (key=CP2 mask=0x4 desc="Block 2 Code Protect")
        setting (req=0x4 value=0x4 desc="Disabled")
            checksum (type=0x0 protregion=0x0-0x0)
        setting (req=0x4 value=0x0 desc="Enabled")
            checksum (type=0x27 protregion=0x4000-0x5fff)
    field (key=CP3 mask=0x8 desc="Block 3 Code Protect")
        setting (req=0x8 value=0x8 desc="Disabled")
            checksum (type=0x0 protregion=0x0-0x0)
        setting (req=0x8 value=0x0 desc="Enabled")
            checksum (type=0x27 protregion=0x6000-0x7fff)
cfgbits (key=CONFIG5H addr=0x300009 unused=0x0)
    field (key=CPB mask=0x40 desc="Boot Block Code Protect")
        setting (req=0x40 value=0x40 desc="Disabled")
            checksum (type=0x0 protregion=0x0-0x0)
        setting (req=0x40 value=0x0 desc="Enabled")
            checksum (type=0x27 protregion=0x0-0x7ff)
    field (key=CPD mask=0x80 desc="Data EEPROM Code Protect")
        setting (req=0x80 value=0x80 desc="Disabled")
        setting (req=0x80 value=0x0 desc="Enabled")
cfgbits (key=CONFIG6L addr=0x30000a unused=0x0)
    field (key=WRT0 mask=0x1 desc="Block 0 Write Protect")
        setting (req=0x1 value=0x1 desc="Disabled")
        setting (req=0x1 value=0x0 desc="Enabled")
    field (key=WRT1 mask=0x2 desc="Block 1 Write Protect")
        setting (req=0x2 value=0x2 desc="Disabled")
        setting (req=0x2 value=0x0 desc="Enabled")
    field (key=WRT2 mask=0x4 desc="Block 2 Write Protect")
        setting (req=0x4 value=0x4 desc="Disabled")
        setting (req=0x4 value=0x0 desc="Enabled")
    field (key=WRT3 mask=0x8 desc="Block 3 Write Protect")
        setting (req=0x8 value=0x8 desc="Disabled")
        setting (req=0x8 value=0x0 desc="Enabled")
cfgbits (key=CONFIG6H addr=0x30000b unused=0x0)
    field (key=WRTC mask=0x20 desc="Configuration Registers Write Protect")
        setting (req=0x20 value=0x20 desc="Disabled")
        setting (req=0x20 value=0x0 desc="Enabled")
    field (key=WRTB mask=0x40 desc="Boot Block Write Protect")
        setting (req=0x40 value=0x40 desc="Disabled")
        setting (req=0x40 value=0x0 desc="Enabled")
    field (key=WRTD mask=0x80 desc="Data EEPROM Write Protect")
        setting (req=0x80 value=0x80 desc="Disabled")
        setting (req=0x80 value=0x0 desc="Enabled")
cfgbits (key=CONFIG7L addr=0x30000c unused=0x0)
    field (key=EBTR0 mask=0x1 desc="Block 0 Table Read Protect")
        setting (req=0x1 value=0x1 desc="Disabled")
        setting (req=0x1 value=0x0 desc="Enabled")
    field (key=EBTR1 mask=0x2 desc="Block 1 Table Read Protect")
        setting (req=0x2 value=0x2 desc="Disabled")
        setting (req=0x2 value=0x0 desc="Enabled")
    field (key=EBTR2 mask=0x4 desc="Block 2 Table Read Protect")
        setting (req=0x4 value=0x4 desc="Disabled")
        setting (req=0x4 value=0x0 desc="Enabled")
    field (key=EBTR3 mask=0x8 desc="Block 3 Table Read Protect")
        setting (req=0x8 value=0x8 desc="Disabled")
        setting (req=0x8 value=0x0 desc="Enabled")
cfgbits (key=CONFIG7H addr=0x30000d unused=0x0)
    field (key=EBTRB mask=0x40 desc="Boot Block Table Read Protect")
        setting (req=0x40 value=0x40 desc="Disabled")
        setting (req=0x40 value=0x0 desc="Enabled")
