######################################################################
#
# MPLAB IDE .dev File Generated by `pic2dev.py'
#
# Device: PIC12F752
# Family: 16xxxx
# Datasheet: 41576
# Programming Spec: 41561
# Date: Tue Apr 30 09:40:18 2013
#
######################################################################


######################################################################
#
# Memory Regions & Other General Device Information
#
######################################################################

vpp (range=10.000-13.000 dflt=13.000)
vdd (range=2.000-5.500 dfltrange=4.500-5.500 nominal=5.000)
pgming (memtech=ee tries=1 lvpthresh=4.500 boundary=4)
    wait (pgm=2500 eedata=6000 cfg=6000 userid=6000 erase=6000 lvpgm=2500 lverase=2500)
    latches (pgm=4 eedata=1 cfg=1 userid=4 rowerase=16)
EraseAlg=1
HWStackDepth=8
breakpoints (numhwbp=1 datacapture=false idbyte=x)
calmem (region=0x2008-0x2009)
userid (region=0x2000-0x2003)
testmem (region=0x2000-0x207f)
devid (region=0x2006-0x2006 idmask=0x3fe0 id=0x1500)
cfgmem (region=0x2007-0x2007)
bkbgvectmem (region=0x2004-0x2004)
pgmmem (region=0x0-0x3ff)
NumBanks=4
MirrorRegs (0xa-0xb 0x8a-0x8b 0x10a-0x10b 0x18a-0x18b)
MirrorRegs (0x81-0x81 0x181-0x181)
MirrorRegs (0x2-0x4 0x82-0x84 0x182-0x184)
MirrorRegs (0x0-0x4 0x100-0x104)
MirrorRegs (0x0-0x0 0x80-0x80 0x180-0x180)
MirrorRegs (0x70-0x7f 0xf0-0xff 0x170-0x17f 0x1f0-0x1ff)
UnusedRegs (0x20-0x3f)
UnusedRegs (0xa0-0xef)
UnusedRegs (0x120-0x16f)
UnusedRegs (0x1a0-0x1ef)

######################################################################
#
# Special Function Registers
#
######################################################################

sfr (key=INDF addr=0x0 size=1 flags=i access='u u u u u u u u')
    reset (por='xxxxxxxx' mclr='xxxxxxxx')
    bit (names='INDF' width='8')
sfr (key=TMR0 addr=0x1 size=1 access='rw rw rw rw rw rw rw rw')
    reset (por='xxxxxxxx' mclr='uuuuuuuu')
    bit (names='TMR0' width='8')
    stimulus (scl=rwb pcfiles=w regfiles=w type=int)
sfr (key=PCL addr=0x2 size=1 access='rw rw rw rw rw rw rw rw')
    reset (por='00000000' mclr='00000000')
    bit (names='PCL' width='8')
    stimulus (scl=rwb pcfiles=rw regfiles=w)
sfr (key=STATUS addr=0x3 size=1 access='rw rw rw r r rw rw rw')
    reset (por='00011xxx' mclr='000qquuu')
    bit (names='IRP RP1 RP0 nTO nPD Z DC C' width='1 1 1 1 1 1 1 1')
sfr (key=FSR addr=0x4 size=1 access='rw rw rw rw rw rw rw rw')
    reset (por='xxxxxxxx' mclr='uuuuuuuu')
    bit (names='FSR' width='8')
    stimulus (scl=rwb pcfiles=rw regfiles=w type=int)
sfr (key=PORTA addr=0x5 size=1 access='u u rw rw r rw rw rw')
    reset (por='--xxxxxx' mclr='--uuuuuu')
    bit (names='- - RA5 RA4 RA3 RA2 RA1 RA0' width='1 1 1 1 1 1 1 1')
    stimulus (scl=rwb pcfiles=rw regfiles=rw)
UnusedRegs (0x6-0x7)
sfr (key=IOCAF addr=0x8 size=1 access='u u rw rw rw rw rw rw')
    reset (por='--000000' mclr='--000000')
    bit (names='- - IOCAF5 IOCAF4 IOCAF3 IOCAF2 IOCAF1 IOCAF0' width='1 1 1 1 1 1 1 1')
UnusedRegs (0x9-0x9)
sfr (key=PCLATH addr=0xa size=1 access='u u u rw rw rw rw rw')
    reset (por='---00000' mclr='---00000')
    bit (names='- - - PCLATH' width='1 1 1 5')
    stimulus (scl=rwb pcfiles=rw regfiles=w type=int)
sfr (key=INTCON addr=0xb size=1 access='rw rw rw rw rw rw rw rw')
    reset (por='00000000' mclr='00000000')
    bit (names='GIE PEIE T0IE INTE IOCIE T0IF INTF IOCIF' width='1 1 1 1 1 1 1 1')
    stimulus (scl=rwb pcfiles=rw regfiles=w)
sfr (key=PIR1 addr=0xc size=1 access='rw rw u u u rw rw rw')
    reset (por='00---000' mclr='00---000')
    bit (names='TMR1GIF ADIF - - - HLTMR1IF TMR2IF TMR1IF' width='1 1 1 1 1 1 1 1')
    stimulus (scl=rwb pcfiles=rw regfiles=w)
sfr (key=PIR2 addr=0xd size=1 access='u u rw rw u rw u rw')
    reset (por='--00-0-0' mclr='--00-0-0')
    bit (names='- - C2IF C1IF - COG1IF - CCP1IF' width='1 1 1 1 1 1 1 1')
UnusedRegs (0xe-0xe)
sfr (key=TMR1 addr=0xf size=2 flags=j)
    bit (names='TMR1' width='16')
    stimulus (scl=rwb regfiles=w type=int)
sfr (key=TMR1L addr=0xf size=1 access='rw rw rw rw rw rw rw rw')
    reset (por='xxxxxxxx' mclr='uuuuuuuu')
    bit (names='TMR1L' width='8')
    stimulus (scl=rwb pcfiles=w regfiles=w type=int)
sfr (key=TMR1H addr=0x10 size=1 access='rw rw rw rw rw rw rw rw')
    reset (por='xxxxxxxx' mclr='uuuuuuuu')
    bit (names='TMR1H' width='8')
    stimulus (scl=rwb pcfiles=w regfiles=w type=int)
sfr (key=T1CON addr=0x11 size=1 access='rw rw rw rw 0 rw u rw')
    reset (por='000000-0' mclr='uuuuuu-u')
    bit (names='TMR1CS T1CKPS reserved nT1SYNC - TMR1ON' width='2 2 1 1 1 1')
sfr (key=T1GCON addr=0x12 size=1 access='rw rw rw rw rw r rw rw')
    reset (por='00000x00' mclr='uuuuuxuu')
    bit (names='TMR1GE T1GPOL T1GTM T1GSPM T1GGO_nDONE T1GVAL T1GSS' width='1 1 1 1 1 1 2')
sfr (key=CCPR1 addr=0x13 size=2 flags=j)
    bit (names='CCPR1' width='16')
    stimulus (scl=rwb regfiles=w type=int)
sfr (key=CCPR1L addr=0x13 size=1 access='rw rw rw rw rw rw rw rw')
    reset (por='xxxxxxxx' mclr='uuuuuuuu')
    bit (names='CCPR1L' width='8')
    stimulus (scl=rwb regfiles=w type=int)
sfr (key=CCPR1H addr=0x14 size=1 access='rw rw rw rw rw rw rw rw')
    reset (por='xxxxxxxx' mclr='uuuuuuuu')
    bit (names='CCPR1H' width='8')
    stimulus (scl=rwb regfiles=w type=int)
sfr (key=CCP1CON addr=0x15 size=1 access='u u rw rw rw rw rw rw')
    reset (por='--000000' mclr='--000000')
    bit (names='- - DC1B CCP1M' width='1 1 2 4')
    stimulus (scl=rwb regfiles=w)
UnusedRegs (0x16-0x1b)
sfr (key=ADRES addr=0x1c size=2 flags=j)
sfr (key=ADRESL addr=0x1c size=1 access='rw rw rw rw rw rw rw rw')
    reset (por='xxxxxxxx' mclr='uuuuuuuu')
    bit (names='ADRESL' width='8')
    stimulus (scl=rwb regfiles=r type=int)
sfr (key=ADRESH addr=0x1d size=1 access='rw rw rw rw rw rw rw rw')
    reset (por='xxxxxxxx' mclr='uuuuuuuu')
    bit (names='ADRESH' width='8')
    stimulus (scl=rwb type=int)
sfr (key=ADCON0 addr=0x1e size=1 access='rw rw rw rw rw rw rw rw')
    reset (por='00000000' mclr='00000000')
    bit (names='ADFM VCFG CHS GO/nDONE ADON' width='1 1 4 1 1')
    stimulus (scl=rwb regfiles=w)
sfr (key=ADCON1 addr=0x1f size=1 access='u rw rw rw u u u u')
    reset (por='-000----' mclr='-000----')
    bit (names='- ADCS - - - -' width='1 3 1 1 1 1')
sfr (key=OPTION_REG addr=0x81 size=1 access='rw rw rw rw rw rw rw rw')
    reset (por='11111111' mclr='11111111')
    bit (names='nRAPU INTEDG T0CS T0SE PSA PS' width='1 1 1 1 1 3')
    stimulus (scl=rwb regfiles=w)
sfr (key=TRISA addr=0x85 size=1 access='u u rw rw rw rw rw rw')
    reset (por='--111111' mclr='--111111')
    bit (names='- - TRISA5 TRISA4 TRISA3 TRISA2 TRISA1 TRISA0' width='1 1 1 1 1 1 1 1')
    stimulus (scl=rwb regfiles=w)
UnusedRegs (0x86-0x87)
sfr (key=IOCAP addr=0x88 size=1 access='u u rw rw rw rw rw rw')
    reset (por='--000000' mclr='--000000')
    bit (names='- - IOCAP5 IOCAP4 IOCAP3 IOCAP2 IOCAP1 IOCAP0' width='1 1 1 1 1 1 1 1')
UnusedRegs (0x89-0x89)
sfr (key=PIE1 addr=0x8c size=1 access='rw rw u u u rw rw rw')
    reset (por='00---000' mclr='00---000')
    bit (names='TMR1GIE ADIE - - - HLTMR1IE TMR2IE TMR1IE' width='1 1 1 1 1 1 1 1')
    stimulus (scl=rwb pcfiles=rw regfiles=w)
sfr (key=PIE2 addr=0x8d size=1 access='u u rw rw u rw u rw')
    reset (por='--00-0-0' mclr='--00-0-0')
    bit (names='- - C2IE C1IE - COG1IE - CCP1IE' width='1 1 1 1 1 1 1 1')
UnusedRegs (0x8e-0x8e)
sfr (key=OSCCON addr=0x8f size=1 access='u u rw rw u rw rw u')
    reset (por='--01-00-' mclr='--uu-uu-')
    bit (names='- - IRCF - HTS LTS -' width='1 1 2 1 1 1 1')
    stimulus (scl=rwb regfiles=w)
sfr (key=FVRCON addr=0x90 size=1 access='rw rw rw rw u u u u')
    reset (por='0000----' mclr='0000----')
    bit (names='FVREN FVRRDY FVRBUFEN FVRBUFSS - - - -' width='1 1 1 1 1 1 1 1')
    stimulus (scl=rwb pcfiles=rw regfiles=w)
sfr (key=DACCON0 addr=0x91 size=1 access='rw rw rw u u rw u u')
    reset (por='000--0--' mclr='000--0--')
    bit (names='DACEN DACRNG DACOE - - DACPSS0 - -' width='1 1 1 1 1 1 1 1')
sfr (key=DACCON1 addr=0x92 size=1 access='u u u rw rw rw rw rw')
    reset (por='---00000' mclr='---00000')
    bit (names='- - - DACR' width='1 1 1 5')
UnusedRegs (0x93-0x9a)
sfr (key=CM2CON0 addr=0x9b size=1 access='rw rw rw rw rw rw rw rw')
    reset (por='00000100' mclr='00000100')
    bit (names='C2ON C2OUT C2OE C2POL C2ZLF C2SP C2HYS C2SYNC' width='1 1 1 1 1 1 1 1')
sfr (key=CM2CON1 addr=0x9c size=1 access='rw rw rw rw u u u rw')
    reset (por='0000---0' mclr='0000---0')
    bit (names='C2INTP C2INTN C2PCH - - - C2NCH0' width='1 1 2 1 1 1 1')
sfr (key=CM1CON0 addr=0x9d size=1 access='rw rw rw rw rw rw rw rw')
    reset (por='00000100' mclr='00000100')
    bit (names='C1ON C1OUT C1OE C1POL C1ZLF C1SP C1HYS C1SYNC' width='1 1 1 1 1 1 1 1')
sfr (key=CM1CON1 addr=0x9e size=1 access='rw rw rw rw u u u rw')
    reset (por='0000---0' mclr='0000---0')
    bit (names='C1INTP C1INTN C1PCH - - - C1NCH0' width='1 1 2 1 1 1 1')
sfr (key=CMOUT addr=0x9f size=1 access='u u u u u u rw rw')
    reset (por='------00' mclr='------00')
    bit (names='- - - - - - MCOUT2 MCOUT1' width='1 1 1 1 1 1 1 1')
sfr (key=LATA addr=0x105 size=1 access='u u rw rw u rw rw rw')
    reset (por='--xx-xxx' mclr='--uu-uuu')
    bit (names='- - LATA5 LATA4 - LATA2 LATA1 LATA0' width='1 1 1 1 1 1 1 1')
UnusedRegs (0x106-0x107)
sfr (key=IOCAN addr=0x108 size=1 access='u u rw rw rw rw rw rw')
    reset (por='--000000' mclr='--000000')
    bit (names='- - IOCAN5 IOCAN4 IOCAN3 IOCAN2 IOCAN1 IOCAN0' width='1 1 1 1 1 1 1 1')
UnusedRegs (0x109-0x109)
sfr (key=WPUA addr=0x10c size=1 access='u u rw rw rw rw rw rw')
    reset (por='--000000' mclr='--000000')
    bit (names='- - WPUA5 WPUA4 WPUA3 WPUA2 WPUA1 WPUA0' width='1 1 1 1 1 1 1 1')
sfr (key=SLRCONA addr=0x10d size=1 access='u u u u u rw u rw')
    reset (por='-----1-1' mclr='-----1-1')
    bit (names='- - - - - SLRA2 - SLRA0' width='1 1 1 1 1 1 1 1')
UnusedRegs (0x10e-0x10e)
sfr (key=PCON addr=0x10f size=1 access='u u u u u u rw rw')
    reset (por='------qq' mclr='------uu')
    bit (names='- - - - - - nPOR nBOR' width='1 1 1 1 1 1 1 1')
sfr (key=TMR2 addr=0x110 size=1 access='rw rw rw rw rw rw rw rw')
    reset (por='00000000' mclr='00000000')
    bit (names='TMR2' width='8')
    stimulus (scl=rwb pcfiles=w regfiles=w type=int)
sfr (key=PR2 addr=0x111 size=1 access='rw rw rw rw rw rw rw rw')
    reset (por='11111111' mclr='11111111')
    bit (names='PR2' width='8')
sfr (key=T2CON addr=0x112 size=1 access='u rw rw rw rw rw rw rw')
    reset (por='-0000000' mclr='-0000000')
    bit (names='- T2OUTPS TMR2ON T2CKPS' width='1 4 1 2')
sfr (key=HLTMR1 addr=0x113 size=1 access='rw rw rw rw rw rw rw rw')
    reset (por='00000000' mclr='00000000')
    bit (names='HLTMR1' width='8')
    stimulus (scl=rwb pcfiles=w regfiles=w type=int)
sfr (key=HLTPR1 addr=0x114 size=1 access='rw rw rw rw rw rw rw rw')
    reset (por='11111111' mclr='11111111')
    bit (names='HLTPR1' width='8')
sfr (key=HLT1CON0 addr=0x115 size=1 access='u rw rw rw rw rw rw rw')
    reset (por='-0000000' mclr='-0000000')
    bit (names='- H1OUTPS H1ON H1CKPS' width='1 4 1 2')
sfr (key=HLT1CON1 addr=0x116 size=1 access='u u u rw rw rw rw rw')
    reset (por='---00000' mclr='---00000')
    bit (names='- - - H1ERS H1FEREN H1REREN' width='1 1 1 3 1 1')
UnusedRegs (0x117-0x11f)
sfr (key=ANSELA addr=0x185 size=1 access='u u rw rw u rw rw rw')
    reset (por='--11-111' mclr='--11-111')
    bit (names='- - ANSA5 ANSA4 - ANSA2 ANSA1 ANSA0' width='1 1 1 1 1 1 1 1')
UnusedRegs (0x186-0x187)
sfr (key=APFCON addr=0x188 size=1 access='u u u rw u rw rw rw')
    reset (por='---0-000' mclr='---0-000')
    bit (names='- - - T1GSEL - COG1FSEL COG1O1SEL COG1O0SEL' width='1 1 1 1 1 1 1 1')
sfr (key=OSCTUNE addr=0x189 size=1 access='u u u rw rw rw rw rw')
    reset (por='---00000' mclr='---uuuuu')
    bit (names='- - - TUN' width='1 1 1 5')
sfr (key=PMCON1 addr=0x18c size=1 access='u u u u u rw rs rs')
    reset (por='-----000' mclr='-----000')
    bit (names='- - - - - WREN WR RD' width='1 1 1 1 1 1 1 1')
    stimulus (scl=rwb pcfiles=rw regfiles=w)
sfr (key=PMCON2 addr=0x18d size=1 access='w w w w w w w w')
    reset (por='--------' mclr='--------')
    bit (names='PMCON2' width='8')
sfr (key=PMADR addr=0x18e size=2 flags=j)
sfr (key=PMADRL addr=0x18e size=1 access='rw rw rw rw rw rw rw rw')
    reset (por='00000000' mclr='00000000')
    bit (names='PMADRL' width='8')
    stimulus (scl=rwb pcfiles=rw regfiles=w)
sfr (key=PMADRH addr=0x18f size=1 access='u u u u u u rw rw')
    reset (por='------00' mclr='------00')
    bit (names='- - - - - - PMADRH' width='1 1 1 1 1 1 2')
    stimulus (scl=rwb pcfiles=rw regfiles=w)
sfr (key=PMDAT addr=0x190 size=2 flags=j)
sfr (key=PMDATL addr=0x190 size=1 access='rw rw rw rw rw rw rw rw')
    reset (por='00000000' mclr='00000000')
    bit (names='PMDATL' width='8')
    stimulus (scl=rwb pcfiles=rw regfiles=rw)
sfr (key=PMDATH addr=0x191 size=1 access='u u rw rw rw rw rw rw')
    reset (por='--000000' mclr='--000000')
    bit (names='- - PMDATH' width='1 1 6')
    stimulus (scl=rwb pcfiles=rw regfiles=rw)
sfr (key=COG1PH addr=0x192 size=1 access='u u u u rw rw rw rw')
    reset (por='----xxxx' mclr='----uuuu')
    bit (names='- - - - G1PH' width='1 1 1 1 4')
sfr (key=COG1BLK addr=0x193 size=1 access='rw rw rw rw rw rw rw rw')
    reset (por='xxxxxxxx' mclr='uuuuuuuu')
    bit (names='G1BLKR G1BLKF' width='4 4')
sfr (key=COG1DB addr=0x194 size=1 access='rw rw rw rw rw rw rw rw')
    reset (por='xxxxxxxx' mclr='uuuuuuuu')
    bit (names='G1DBR G1DBF' width='4 4')
sfr (key=COG1CON0 addr=0x195 size=1 access='rw rw rw rw rw rw rw rw')
    reset (por='00000000' mclr='00000000')
    bit (names='G1EN G1OE1 G1OE0 G1POL1 G1POL0 G1LD G1CS' width='1 1 1 1 1 1 2')
sfr (key=COG1CON1 addr=0x196 size=1 access='rw rw rw rw rw rw rw rw')
    reset (por='00000000' mclr='00000000')
    bit (names='G1FSIM G1RSIM G1FS G1RS' width='1 1 3 3')
sfr (key=COG1ASD addr=0x197 size=1 access='rw rw rw rw rw rw rw rw')
    reset (por='00000000' mclr='00000000')
    bit (names='G1ASDE G1ARSEN G1ASDL1 G1ASDL0 G1ASDSHLT G1ASDSC2 G1ASDSC1 G1ASDSFLT' width='1 1 1 1 1 1 1 1')
UnusedRegs (0x198-0x19f)

######################################################################
#
# Non Memory-Mapped Registers
#
# (Conditionally visible SFRs appear as NMMRs in the "Special Function
# Registers" section.)
#
######################################################################

HasNMMR=1
nmmr (key=WREG addr=0x0 size=1 access='rw rw rw rw rw rw rw rw')
    reset (por='00000000' mclr='00000000')
nmmr (key=STKPTR addr=0x1 size=1 flags=h access='rw rw rw rw rw rw rw')
    reset (por='00000000' mclr='00000000')
NMMRObjSize=2

######################################################################
#
# Configuration Registers
#
######################################################################

cfgbits (key=CONFIG addr=0x2007 unused=0x3000)
    illegal (mask=0x48 value=0x48 msg="Current settings of PWRT and BOD are in conflict")
    field (key=FOSC0 mask=0x1 desc="FOSC: Oscillator Selection bit")
        setting (req=0x1 value=0x1 desc="EC oscillator mode.  CLKIN function on RA5/CLKIN")
        setting (req=0x1 value=0x0 desc="Internal oscillator mode.  I/O function on RA5/CLKIN")
    field (key=WDTE mask=0x8 desc="Watchdog Timer Enable bit")
        setting (req=0x8 value=0x8 desc="Enabled")
        setting (req=0x8 value=0x0 desc="Disabled")
    field (key=PWRTE mask=0x10 desc="Power-up Timer Enable bit")
        setting (req=0x10 value=0x10 desc="Disabled")
        setting (req=0x10 value=0x0 desc="Enabled")
    field (key=MCLRE mask=0x20 desc="MCLR/VPP Pin Function Select bit")
        setting (req=0x20 value=0x20 desc="Enabled")
        setting (req=0x20 value=0x0 desc="Disabled")
    field (key=CP mask=0x40 desc="Code Protection bit")
        setting (req=0x40 value=0x40 desc="Disabled")
            checksum (type=0x0 protregion=0x0-0x0)
        setting (req=0x40 value=0x0 desc="Enabled")
            checksum (type=0x27 protregion=0x0-0x3ff)
    field (key=BOREN mask=0x300 desc="Brown-out Reset Enable bits")
        setting (req=0x300 value=0x300 desc="BOR enabled")
        setting (req=0x300 value=0x200 desc="BOR enabled during operation and disabled in Sleep")
        setting (req=0x200 value=0x0 desc="BOR disabled")
    field (key=WRT mask=0xc00 desc="Flash Program Memory Self Write Enable bit")
        setting (req=0xc00 value=0xc00 desc="Disabled")
        setting (req=0xc00 value=0x800 desc="000h to 0FFh self-write protected")
        setting (req=0xc00 value=0x400 desc="000h to 1FFh self-write protected")
        setting (req=0xc00 value=0x0 desc="000h to 3FFh self-write protected")
    field (key=CKLOUTEN mask=0x1000 desc="Clock Out Enable bit")
        setting (req=0x1000 value=0x1000 desc="Disabled")
        setting (req=0x1000 value=0x0 desc="Enabled")
    field (key=DEBUG mask=0x2000 desc="Debug Mode Enable bit" flags=h)
        setting (req=0x2000 value=0x2000 desc="Disabled")
        setting (req=0x2000 value=0x0 desc="Enabled")
