######################################################################
#
# MPLAB IDE .dev File Generated by `pic2dev.py'
#
# Device: PIC12CE518
# Family: 16c5x
# Datasheet: 40139
# Programming Spec: 30557
# Date: Tue Apr 30 09:40:04 2013
#
######################################################################


######################################################################
#
# Memory Regions & Other General Device Information
#
######################################################################

vpp (range=12.750-13.250 dflt=13.000)
vdd (range=2.500-5.500 dfltrange=3.000-5.500 nominal=5.000)
pgming (memtech=eprom ovrpgm=11 tries=8)
    wait (pgm=100 cfg=100 userid=100)
HWStackDepth=2
calmem (region=0x1ff-0x1ff)
testmem (region=0x200-0x23f)
userid (region=0x200-0x203)
cfgmem (region=0xfff-0xfff)
pgmmem (region=0x0-0x1ff)
NumBanks=1

######################################################################
#
# Special Function Registers
#
######################################################################

sfr (key=INDF addr=0x0 size=1 flags=i access='u u u u u u u u')
    reset (por='--------' mclr='--------')
    bit (names='INDF' width='8')
sfr (key=TMR0 addr=0x1 size=1 access='rw rw rw rw rw rw rw rw')
    reset (por='xxxxxxxx' mclr='uuuuuuuu')
    bit (names='TMR0' width='8')
    stimulus (scl=rwb pcfiles=w regfiles=w type=int)
sfr (key=PCL addr=0x2 size=1 access='rw rw rw rw rw rw rw rw')
    reset (por='11111111' mclr='11111111')
    bit (names='PCL' width='8')
    stimulus (scl=rwb pcfiles=rw regfiles=w)
sfr (key=STATUS addr=0x3 size=1 access='rw u rw r r rw rw rw')
    reset (por='0-011xxx' mclr='q-0qquuu')
    bit (names='GPWUF - PA0 nTO nPD Z DC C' width='1 1 1 1 1 1 1 1')
sfr (key=FSR addr=0x4 size=1 access='r r r rw rw rw rw rw')
    reset (por='111xxxxx' mclr='111uuuuu')
    bit (names='FSR' width='8')
    stimulus (scl=rwb pcfiles=rw regfiles=w)
sfr (key=OSCCAL addr=0x5 size=1 access='rw rw rw rw rw rw u u')
    reset (por='100000--' mclr='uuuuuu--')
    bit (names='CAL - -' width='6 1 1')
sfr (key=GPIO addr=0x6 size=1 access='w w rw rw r rw rw rw')
    reset (por='11xxxxxx' mclr='11uuuuuu')
    bit (names='SCL SDA GP5 GP4 GP3 GP2 GP1 GP0' width='1 1 1 1 1 1 1 1')
    bit (tag=scl names='GP' width='8')
    stimulus (scl=rwb pcfiles=rw regfiles=rw)

######################################################################
#
# Non Memory-Mapped Registers
#
# (Conditionally visible SFRs appear as NMMRs in the "Special Function
# Registers" section.)
#
######################################################################

HasNMMR=1
nmmr (key=WREG addr=0x0 size=1 access='rw rw rw rw rw rw rw rw')
    reset (por='qqqqqqxx' mclr='qqqqqquu')
    bit (names='WREG' width='8')
nmmr (key=STKPTR addr=0x1 size=1 flags=h access='rw rw rw rw rw rw rw rw')
    reset (por='00000000' mclr='00000000')
    bit (names='STKPTR' width='8')
nmmr (key=TRIS addr=0x3 size=1 access='u u rw rw rw rw rw rw')
    reset (por='--111111' mclr='--111111')
    bit (names='- - TRIS5 TRIS4 TRIS3 TRIS2 TRIS1 TRIS0' width='1 1 1 1 1 1 1 1')
nmmr (key=OPTION_REG addr=0x5 size=1 access='rw rw rw rw rw rw rw rw')
    reset (por='11111111' mclr='11111111')
    bit (names='nGPWU nGPPU T0CS T0SE PSA PS' width='1 1 1 1 1 3')
NMMRObjSize=4

######################################################################
#
# Configuration Registers
#
######################################################################

cfgbits (key=CONFIG addr=0xfff unused=0xfe0)
    field (key=OSC mask=0x3 desc="Oscillator selection bits")
        setting (req=0x3 value=0x3 desc="external RC oscillator")
        setting (req=0x3 value=0x0 desc="LP oscillator")
        setting (req=0x3 value=0x1 desc="XT oscillator")
        setting (req=0x3 value=0x2 desc="internal RC oscillator")
    field (key=WDT mask=0x4 desc="Watchdog timer enable bit")
        setting (req=0x4 value=0x4 desc="Enabled")
        setting (req=0x4 value=0x0 desc="Disabled")
    field (key=CP mask=0x8 desc="Code protection bit")
        setting (req=0x8 value=0x8 desc="Disabled")
            checksum (type=0x0 protregion=0x0-0x0)
        setting (req=0x8 value=0x0 desc="Enabled")
            checksum (type=0x20 protregion=0x40-0x1fe)
    field (key=MCLRE mask=0x10 desc="MCLR enable bit")
        setting (req=0x10 value=0x10 desc="Enabled")
        setting (req=0x10 value=0x0 desc="Disabled")
