######################################################################
#
# MPLAB IDE .dev File Generated by `pic2dev.py'
#
# Device: PIC16F721
# Family: 16xxxx
# Datasheet: 41430
# Programming Spec: 41409
# Date: Tue Apr 30 09:41:17 2013
#
######################################################################


######################################################################
#
# Memory Regions & Other General Device Information
#
######################################################################

vpp (range=8.000-9.000 dflt=8.500)
vdd (range=2.100-5.500 dfltrange=2.500-5.500 nominal=5.000)
pgming (memtech=ee tries=1 lvpthresh=2.700 boundary=8)
    wait (pgm=2500 eedata=8000 cfg=5000 userid=2500 erase=6000 lvpgm=2500)
    latches (pgm=32 eedata=1 cfg=1 userid=1 rowerase=32)
EraseAlg=1
HWStackDepth=8
breakpoints (numhwbp=1 datacapture=false idbyte=x)
testmem (region=0x2000-0x21ff)
userid (region=0x2000-0x2003)
devid (region=0x2006-0x2006 idmask=0x3fe0 id=0x1c20)
cfgmem (region=0x2007-0x2008)
bkbgvectmem (region=0x2004-0x2004)
pgmmem (region=0x0-0xfff)
NumBanks=4
MirrorRegs (0xa-0xb 0x8a-0x8b 0x10a-0x10b 0x18a-0x18b)
MirrorRegs (0x81-0x81 0x181-0x181)
MirrorRegs (0x1-0x1 0x101-0x101)
MirrorRegs (0x2-0x4 0x82-0x84 0x102-0x104 0x182-0x184)
MirrorRegs (0x0-0x0 0x80-0x80 0x100-0x100 0x180-0x180)
MirrorRegs (0x70-0x7f 0xf0-0xff 0x170-0x17f 0x1f0-0x1ff)
UnusedRegs (0x1a0-0x1ef)

######################################################################
#
# Special Function Registers
#
######################################################################

sfr (key=INDF addr=0x0 size=1 flags=i access='u u u u u u u u')
    reset (por='xxxxxxxx' mclr='xxxxxxxx')
    bit (names='INDF' width='8')
sfr (key=TMR0 addr=0x1 size=1 access='rw rw rw rw rw rw rw rw')
    reset (por='xxxxxxxx' mclr='uuuuuuuu')
    bit (names='TMR0' width='8')
    stimulus (scl=rwb pcfiles=w regfiles=w type=int)
sfr (key=PCL addr=0x2 size=1 access='rw rw rw rw rw rw rw rw')
    reset (por='00000000' mclr='00000000')
    bit (names='PCL' width='8')
    stimulus (scl=rwb pcfiles=rw regfiles=w)
sfr (key=STATUS addr=0x3 size=1 access='rw rw rw r r rw rw rw')
    reset (por='00011xxx' mclr='000qquuu')
    bit (names='IRP RP nTO nPD Z DC C' width='1 2 1 1 1 1 1')
sfr (key=FSR addr=0x4 size=1 access='rw rw rw rw rw rw rw rw')
    reset (por='xxxxxxxx' mclr='uuuuuuuu')
    bit (names='FSR' width='8')
    stimulus (scl=rwb pcfiles=rw regfiles=w type=int)
sfr (key=PORTA addr=0x5 size=1 access='u u rw rw rw rw rw rw')
    reset (por='--xxxxxx' mclr='--uuuuuu')
    bit (names='- - RA5 RA4 RA3 RA2 RA1 RA0' width='1 1 1 1 1 1 1 1')
    bit (tag=scl names='RA' width='8')
    stimulus (scl=rwb pcfiles=rw regfiles=rw)
sfr (key=PORTB addr=0x6 size=1 access='rw rw rw rw u u u u')
    reset (por='xxxx----' mclr='uuuu----')
    bit (names='RB7 RB6 RB5 RB4 - - - -' width='1 1 1 1 1 1 1 1')
    bit (tag=scl names='RB' width='8')
    stimulus (scl=rwb pcfiles=rw regfiles=rw)
sfr (key=PORTC addr=0x7 size=1 access='rw rw rw rw rw rw rw rw')
    reset (por='xxxxxxxx' mclr='uuuuuuuu')
    bit (names='RC7 RC6 RC5 RC4 RC3 RC2 RC1 RC0' width='1 1 1 1 1 1 1 1')
    bit (tag=scl names='RC' width='8')
    stimulus (scl=rwb pcfiles=rw regfiles=rw)
UnusedRegs (0x8-0x9)
sfr (key=PCLATH addr=0xa size=1 access='u u u rw rw rw rw rw')
    reset (por='---00000' mclr='---00000')
    bit (names='- - - PCLATH' width='1 1 1 5')
    stimulus (scl=rwb pcfiles=rw regfiles=w type=int)
sfr (key=INTCON addr=0xb size=1 access='rw rw rw rw rw rw rw rw')
    reset (por='0000000x' mclr='0000000x')
    bit (names='GIE PEIE TMR0IE INTE RABIE TMR0IF INTF RABIF' width='1 1 1 1 1 1 1 1')
    stimulus (scl=rwb pcfiles=rw regfiles=w)
sfr (key=PIR1 addr=0xc size=1 access='rw rw r r rw rw rw rw')
    reset (por='00000000' mclr='00000000')
    bit (names='TMR1GIF ADIF RCIF TXIF SSPIF CCP1IF TMR2IF TMR1IF' width='1 1 1 1 1 1 1 1')
    bit (tag=scl names='PSPIF ADIF - - SSPIF CCP1IF TMR2IF TMR1IF' width='1 1 1 1 1 1 1 1')
    stimulus (scl=rwb pcfiles=rw regfiles=w)
UnusedRegs (0xd-0xd)
sfr (key=TMR1 addr=0xe size=2 flags=j)
    bit (names='TMR1' width='16')
    stimulus (scl=rwb regfiles=w type=int)
sfr (key=TMR1L addr=0xe size=1 access='rw rw rw rw rw rw rw rw')
    reset (por='xxxxxxxx' mclr='uuuuuuuu')
    bit (names='TMR1L' width='8')
    stimulus (scl=rwb pcfiles=w regfiles=w type=int)
sfr (key=TMR1H addr=0xf size=1 access='rw rw rw rw rw rw rw rw')
    reset (por='xxxxxxxx' mclr='uuuuuuuu')
    bit (names='TMR1H' width='8')
    stimulus (scl=rwb pcfiles=w regfiles=w type=int)
sfr (key=T1CON addr=0x10 size=1 access='rw rw rw rw u rw u rw')
    reset (por='0000-0-0' mclr='uuuu-u-u')
    bit (names='TMR1CS T1CKPS - T1SYNC - TMR1ON' width='2 2 1 1 1 1')
    stimulus (scl=rwb regfiles=w)
sfr (key=TMR2 addr=0x11 size=1 access='rw rw rw rw rw rw rw rw')
    reset (por='00000000' mclr='00000000')
    bit (names='TMR2' width='8')
    stimulus (scl=rwb pcfiles=w regfiles=w type=int)
sfr (key=T2CON addr=0x12 size=1 access='u rw rw rw rw rw rw rw')
    reset (por='-0000000' mclr='-0000000')
    bit (names='- TOUTPS TMR2ON T2CKPS' width='1 4 1 2')
    stimulus (scl=rwb regfiles=w)
sfr (key=SSPBUF addr=0x13 size=1 access='rw rw rw rw rw rw rw rw')
    reset (por='xxxxxxxx' mclr='uuuuuuuu')
    bit (names='SSPBUF' width='8')
    stimulus (scl=rwb pcfiles=rw regfiles=rw type=int)
sfr (key=SSPCON addr=0x14 size=1 access='rw rw rw rw rw rw rw rw')
    reset (por='00000000' mclr='00000000')
    bit (names='WCOL SSPOV SSPEN CKP SSPM' width='1 1 1 1 4')
    stimulus (scl=rwb pcfiles=rw regfiles=w)
sfr (key=CCPR1 addr=0x15 size=2 flags=j)
    bit (names='CCPR1' width='16')
    stimulus (scl=rwb regfiles=w type=int)
sfr (key=CCPR1L addr=0x15 size=1 access='rw rw rw rw rw rw rw rw')
    reset (por='xxxxxxxx' mclr='uuuuuuuu')
    bit (names='CCPR1L' width='8')
    stimulus (scl=rwb regfiles=w type=int)
sfr (key=CCPR1H addr=0x16 size=1 access='rw rw rw rw rw rw rw rw')
    reset (por='xxxxxxxx' mclr='uuuuuuuu')
    bit (names='CCPR1H' width='8')
    stimulus (scl=rwb regfiles=w type=int)
sfr (key=CCP1CON addr=0x17 size=1 access='u u rw rw rw rw rw rw')
    reset (por='--000000' mclr='--000000')
    bit (names='- - DC1 B1 CCP1M' width='1 1 1 1 4')
    stimulus (scl=rwb regfiles=w)
sfr (key=RCSTA addr=0x18 size=1 access='rw rw rw rw rw r r r')
    reset (por='0000000x' mclr='0000000x')
    bit (names='SPEN RX9 SREN CREN ADDEN FERR OERR RX9D' width='1 1 1 1 1 1 1 1')
    stimulus (scl=rwb regfiles=w)
sfr (key=TXREG addr=0x19 size=1 access='rw rw rw rw rw rw rw rw')
    reset (por='00000000' mclr='00000000')
    bit (names='TXREG' width='8')
    stimulus (scl=rwb regfiles=w)
sfr (key=RCREG addr=0x1a size=1 access='r r r r r r r r')
    reset (por='00000000' mclr='00000000')
    bit (names='RCREG' width='8')
    stimulus (scl=rb regfiles=rp)
UnusedRegs (0x1b-0x1d)
sfr (key=ADRES addr=0x1e size=1 access='rw rw rw rw rw rw rw rw')
    reset (por='xxxxxxxx' mclr='uuuuuuuu')
    bit (names='ADRES' width='8')
    stimulus (scl=rwb regfiles=r type=int)
sfr (key=ADCON0 addr=0x1f size=1 access='u u rw rw rw rw rw rw')
    reset (por='--000000' mclr='--000000')
    bit (names='- - CHS GO/nDONE ADON' width='1 1 4 1 1')
    bit (tag=scl names='- - CHS GO_nDONE ADON' width='1 1 4 1 1')
    stimulus (scl=rwb regfiles=w)
sfr (key=OPTION_REG addr=0x81 size=1 access='rw rw rw rw rw rw rw rw')
    reset (por='11111111' mclr='11111111')
    bit (names='nRABPU INTEDG T0CS T0SE PSA PS' width='1 1 1 1 1 3')
    stimulus (scl=rwb regfiles=w)
sfr (key=TRISA addr=0x85 size=1 access='u u rw rw u rw rw rw')
    reset (por='--11-111' mclr='--11-111')
    bit (names='- - TRISA5 TRISA4 - TRISA2 TRISA1 TRISA0' width='1 1 1 1 1 1 1 1')
    bit (tag=scl names='TRISA' width='8')
    stimulus (scl=rwb regfiles=w)
sfr (key=TRISB addr=0x86 size=1 access='rw rw rw rw u u u u')
    reset (por='1111----' mclr='1111----')
    bit (names='TRISB7 TRISB6 TRISB5 TRISB4 - - - -' width='1 1 1 1 1 1 1 1')
    bit (tag=scl names='TRISB' width='8')
    stimulus (scl=rwb regfiles=w)
sfr (key=TRISC addr=0x87 size=1 access='rw rw rw rw rw rw rw rw')
    reset (por='11111111' mclr='11111111')
    bit (names='TRISC7 TRISC6 TRISC5 TRISC4 TRISC3 TRISC2 TRISC1 TRISC0' width='1 1 1 1 1 1 1 1')
    bit (tag=scl names='TRISC' width='8')
    stimulus (scl=rwb regfiles=w)
UnusedRegs (0x88-0x89)
sfr (key=PIE1 addr=0x8c size=1 access='rw rw rw rw rw rw rw rw')
    reset (por='00000000' mclr='00000000')
    bit (names='TMR1GIE ADIE RCIE TXIE SSPIE CCP1IE TMR2IE TMR1IE' width='1 1 1 1 1 1 1 1')
    stimulus (scl=rwb pcfiles=rw regfiles=w)
UnusedRegs (0x8d-0x8d)
sfr (key=PCON addr=0x8e size=1 access='u u u u u u rw rw')
    reset (por='------qq' mclr='------uu')
    bit (names='- - - - - - nPOR nBOR' width='1 1 1 1 1 1 1 1')
    stimulus (scl=rwb regfiles=w)
sfr (key=T1GCON addr=0x8f size=1 access='rw rw rw rw rw r rw rw')
    reset (por='00000x00' mclr='uuuuuxuu')
    bit (names='TMR1GE T1GPOL T1GTM T1GSPM T1GGO_DONE T1GVAL T1GSS' width='1 1 1 1 1 1 2')
sfr (key=OSCCON addr=0x90 size=1 access='u u rw rw rw rw u u')
    reset (por='--10qq--' mclr='--10qq--')
    bit (names='- - IRCF ICSL ICSS - -' width='1 1 2 1 1 1 1')
sfr (key=OSCTUNE addr=0x91 size=1 access='u u rw rw rw rw rw rw')
    reset (por='--000000' mclr='--000000')
    bit (names='- - TUN' width='1 1 6')
    stimulus (scl=rwb pcfiles=rw regfiles=w)
sfr (key=PR2 addr=0x92 size=1 access='rw rw rw rw rw rw rw rw')
    reset (por='11111111' mclr='11111111')
    bit (names='PR2' width='8')
    stimulus (scl=rwb regfiles=w type=int)
sfr (key=SSPADD addr=0x93 size=1 access='rw rw rw rw rw rw rw rw')
    reset (por='00000000' mclr='00000000')
    bit (names='ADD' width='8')
    stimulus (scl=rwb pcfiles=rw regfiles=w type=int)
nmmr (key=SSPMSK mapaddr=0x93 addr=0x2 size=1 access='rw rw rw rw rw rw rw rw')
    reset (por='11111111' mclr='11111111')
    bit (names='MSK' width='8')
    stimulus (scl=rwb pcfiles=rw regfiles=w type=int)
sfr (key=SSPSTAT addr=0x94 size=1 access='rw rw rw rw rw rw rw rw')
    reset (por='00000000' mclr='00000000')
    bit (names='SMP CKE D/nA P S R/nW UA BF' width='1 1 1 1 1 1 1 1')
    bit (tag=scl names='SMP CKE D_nA P S R_nW UA BF' width='1 1 1 1 1 1 1 1')
    stimulus (scl=rwb pcfiles=rw regfiles=rw)
sfr (key=WPUA addr=0x95 size=1 access='u u rw rw rw rw rw rw')
    reset (por='--111111' mclr='--111111')
    bit (names='- - WPUA5 WPUA4 WPUA3 WPUA2 WPUA1 WPUA0' width='1 1 1 1 1 1 1 1')
sfr (key=IOCA addr=0x96 size=1 access='u u rw rw rw rw rw rw')
    reset (por='--000000' mclr='--000000')
    bit (names='- - IOCA5 IOCA4 IOCA3 IOCA2 IOCA1 IOCA0' width='1 1 1 1 1 1 1 1')
UnusedRegs (0x97-0x97)
sfr (key=TXSTA addr=0x98 size=1 access='rw rw rw rw u rw r rw')
    reset (por='0000-010' mclr='0000-010')
    bit (names='CSRC TX9 TXEN SYNC - BRGH TRMT TX9D' width='1 1 1 1 1 1 1 1')
    stimulus (scl=rwb regfiles=w)
sfr (key=SPBRG addr=0x99 size=1 access='rw rw rw rw rw rw rw rw')
    reset (por='00000000' mclr='00000000')
    bit (names='SPBRG' width='8')
    stimulus (scl=rwb regfiles=w)
UnusedRegs (0x9a-0x9c)
sfr (key=FVRCON addr=0x9d size=1 access='rw rw rw rw u u rw rw')
    reset (por='q0xx--00' mclr='q0xx--00')
    bit (names='FVRRDY FVREN TSEN TSRNG - - ADFVR1 ADFVR0' width='1 1 1 1 1 1 1 1')
UnusedRegs (0x9e-0x9e)
sfr (key=ADCON1 addr=0x9f size=1 access='u rw rw rw u u u u')
    reset (por='-000----' mclr='-000----')
    bit (names='- ADCS2 ADCS1 ADCS0 - - - -' width='1 1 1 1 1 1 1 1')
    stimulus (scl=rwb regfiles=w)
UnusedRegs (0x105-0x109)
sfr (key=PMDATL addr=0x10c size=1 access='rw rw rw rw rw rw rw rw')
    reset (por='xxxxxxxx' mclr='uuuuuuuu')
    bit (names='PMDATL' width='8')
    stimulus (scl=rwb pcfiles=rw regfiles=rw)
sfr (key=PMADRL addr=0x10d size=1 access='rw rw rw rw rw rw rw rw')
    reset (por='00000000' mclr='00000000')
    bit (names='PMADRL' width='8')
    stimulus (scl=rwb pcfiles=rw regfiles=w)
sfr (key=PMDATH addr=0x10e size=1 access='u u rw rw rw rw rw rw')
    reset (por='--xxxxxx' mclr='--uuuuuu')
    bit (names='- - PMDATH' width='1 1 6')
    stimulus (scl=rwb pcfiles=rw regfiles=rw)
sfr (key=PMADRH addr=0x10f size=1 access='u u u rw rw rw rw rw')
    reset (por='---00000' mclr='---00000')
    bit (names='- - - PMADRH' width='1 1 1 5')
    stimulus (scl=rwb pcfiles=rw regfiles=w)
UnusedRegs (0x110-0x114)
sfr (key=WPUB addr=0x115 size=1 access='rw rw rw rw u u u u')
    reset (por='1111----' mclr='1111----')
    bit (names='WPUB7 WPUB6 WPUB5 WPUB4 - - - -' width='1 1 1 1 1 1 1 1')
sfr (key=IOCB addr=0x116 size=1 access='rw rw rw rw u u u u')
    reset (por='0000----' mclr='0000----')
    bit (names='IOCB7 IOCB6 IOCB5 IOCB4 - - - -' width='1 1 1 1 1 1 1 1')
UnusedRegs (0x117-0x11f)
sfr (key=ANSELA addr=0x185 size=1 access='u u rw rw u rw rw rw')
    reset (por='--11-111' mclr='--11-111')
    bit (names='- - ANSA5 ANSA4 - ANSA2 ANSA1 ANSA0' width='1 1 1 1 1 1 1 1')
    stimulus (scl=rwb)
sfr (key=ANSELB addr=0x186 size=1 access='u u rw rw u u u u')
    reset (por='--11----' mclr='--11----')
    bit (names='- - ANSB5 ANSB4 - - - -' width='1 1 1 1 1 1 1 1')
    stimulus (scl=rwb)
sfr (key=ANSELC addr=0x187 size=1 access='rw rw u u rw rw rw rw')
    reset (por='11--1111' mclr='11--1111')
    bit (names='ANSC7 ANSC6 - - ANSC3 ANSC2 ANSC1 ANSC0' width='1 1 1 1 1 1 1 1')
UnusedRegs (0x188-0x189)
sfr (key=PMCON1 addr=0x18c size=1 access='u rw rw rw u rw rw rw')
    reset (por='1000-000' mclr='1000-000')
    bit (names='- CFGS LWLO FREE - WREN WR RD' width='1 1 1 1 1 1 1 1')
    stimulus (scl=rwb)
sfr (key=PMCON2 addr=0x18d size=1 access='u u u u u u u u')
    reset (por='--------' mclr='--------')
    bit (names='- - - - - - - -' width='1 1 1 1 1 1 1 1')
UnusedRegs (0x18e-0x19f)

######################################################################
#
# Non Memory-Mapped Registers
#
# (Conditionally visible SFRs appear as NMMRs in the "Special Function
# Registers" section.)
#
######################################################################

HasNMMR=1
nmmr (key=WREG addr=0x0 size=1 access='rw rw rw rw rw rw rw rw')
    reset (por='00000000' mclr='00000000')
nmmr (key=STKPTR addr=0x1 size=1 flags=h access='rw rw rw rw rw rw rw')
    reset (por='00000000' mclr='00000000')
NMMRObjSize=3

######################################################################
#
# Configuration Registers
#
######################################################################

cfgbits (key=CONFIG1 addr=0x2007 unused=0x3000)
    field (key=FOSC mask=0x3 desc="Oscillator Selection bits")
        setting (req=0x3 value=0x3 desc="EC oscillator: CLKO function on RA4/CLKO pin, CLKI on RA5/CLKI")
        setting (req=0x3 value=0x2 desc="EC oscillator: I/O function on RA4/CLKO pin, CLKI on RA5/CLKI")
        setting (req=0x3 value=0x1 desc="INTOSC oscillator: CLKO function on RA4/CLKO pin, I/O function on RA5/CLKI")
        setting (req=0x3 value=0x0 desc="INTOSCIO oscillator: I/O function on RA4/CLKO pin, I/O function on RA5/CLKI")
    field (key=WDTE mask=0x8 desc="Watchdog Timer Enable bit")
        setting (req=0x8 value=0x0 desc="Disabled")
        setting (req=0x8 value=0x8 desc="Enabled")
    field (key=PWRTE mask=0x10 desc="Power-up Timer Enable bit")
        setting (req=0x10 value=0x0 desc="Enabled")
        setting (req=0x10 value=0x10 desc="Disabled")
    field (key=MCLRE mask=0x20 desc="RA3/MCLR/VPP Pin Function Select bit")
        setting (req=0x20 value=0x20 desc="Enabled")
        setting (req=0x20 value=0x0 desc="Disabled")
    field (key=CP mask=0x40 desc="Flash Program Memory Code Protection bit")
        setting (req=0x40 value=0x0 desc="Enabled")
            checksum (type=0x20 protregion=0x0-0xfff)
        setting (req=0x40 value=0x40 desc="Disabled")
            checksum (type=0x0 protregion=0x0-0x0)
    field (key=BOREN mask=0x300 desc="Brown-out Reset Enable bits")
        setting (req=0x300 value=0x0 desc="Disabled")
        setting (req=0x300 value=0x200 desc="Brown-out Reset enabled during operation and disabled in Sleep")
        setting (req=0x300 value=0x300 desc="Enabled")
    field (key=PLLEN mask=0x1000 desc="INTOSC PLLEN Enable Bit")
        setting (req=0x1000 value=0x0 desc="Disabled")
        setting (req=0x1000 value=0x1000 desc="Enabled")
    field (key=DEBUG mask=0x2000 desc="Debugger Mode" flags=h)
        setting (req=0x2000 value=0x0 desc="Enabled")
        setting (req=0x2000 value=0x2000 desc="Disabled")
cfgbits (key=CONFIG2 addr=0x2008 unused=0x0)
    field (key=WRTEN mask=0x3 desc="Flash memory self-write protection bits")
        setting (req=0x3 value=0x3 desc="Disabled")
        setting (req=0x3 value=0x2 desc="0h to 1FFh of flash memory write protected, 200h to FFFh may be modified")
        setting (req=0x3 value=0x1 desc="0h to 7FFh of flash memory write protected, 800h to FFFh may be modified")
        setting (req=0x3 value=0x0 desc="0h to FFFh of flash memory write protected, no address may be modified")
    field (key=VCAPEN mask=0x10 desc="..." flags=h)
        setting (req=0x10 value=0x10 desc="Disabled")
