######################################################################
#
# MPLAB IDE .dev File Generated by `pic2dev.py'
#
# Device: PIC12F635
# Family: 16xxxx
# Datasheet: 41232
# Programming Spec: 41204
# Date: Tue Apr 30 09:40:18 2013
#
######################################################################


######################################################################
#
# Memory Regions & Other General Device Information
#
######################################################################

vpp (range=10.000-12.000 dflt=11.000)
vdd (range=2.000-5.500 dfltrange=3.000-5.500 nominal=5.000)
pgming (memtech=ee tries=1 lvpthresh=4.500)
    wait (pgm=2500 eedata=6000 cfg=6000 userid=6000 erase=6000 lvpgm=2500 lverase=2500)
    latches (pgm=4 eedata=1 cfg=1 userid=1 rowerase=16)
EraseAlg=1
HWStackDepth=8
breakpoints (numhwbp=1 datacapture=false idbyte=x)
calmem (region=0x2008-0x2009)
userid (region=0x2000-0x2003)
testmem (region=0x2000-0x203f)
devid (region=0x2006-0x2006 idmask=0x3fe0 id=0xfa0)
cfgmem (region=0x2007-0x2007)
eedata (region=0x0-0x7f)
bkbgvectmem (region=0x2004-0x2004)
pgmmem (region=0x0-0x3ff)
NumBanks=4
MirrorRegs (0xa-0xa 0x10a-0x10a)
MirrorRegs (0x1-0x1 0x101-0x101)
MirrorRegs (0x85-0x85 0x185-0x185)
MirrorRegs (0xa-0xb 0x8a-0x8b)
MirrorRegs (0x81-0x81 0x181-0x181)
MirrorRegs (0x0-0x0 0x80-0x80 0x100-0x100 0x180-0x180)
MirrorRegs (0xb-0xb 0x10b-0x10b 0x18b-0x18b)
MirrorRegs (0x2-0x4 0x82-0x84 0x102-0x104 0x182-0x184)
MirrorRegs (0x8a-0x8a 0x18a-0x18a)
MirrorRegs (0x5-0x5 0x105-0x105)
MirrorRegs (0x70-0x7f 0xf0-0xff 0x170-0x17f 0x1f0-0x1ff)
UnusedRegs (0x20-0x3f)
UnusedRegs (0xa0-0xef)
UnusedRegs (0x120-0x16f)
UnusedRegs (0x1a0-0x1ef)

######################################################################
#
# Special Function Registers
#
######################################################################

sfr (key=INDF addr=0x0 size=1 flags=i access='u u u u u u u u')
    reset (por='--------' mclr='--------')
    bit (names='INDF' width='8')
sfr (key=TMR0 addr=0x1 size=1 access='rw rw rw rw rw rw rw rw')
    reset (por='xxxxxxxx' mclr='uuuuuuuu')
    bit (names='TMR0' width='8')
    stimulus (scl=rwb pcfiles=w regfiles=w type=int)
sfr (key=PCL addr=0x2 size=1 access='rw rw rw rw rw rw rw rw')
    reset (por='00000000' mclr='00000000')
    bit (names='PCL' width='8')
    stimulus (scl=rwb pcfiles=rw regfiles=w)
sfr (key=STATUS addr=0x3 size=1 access='rw rw rw r r rw rw rw')
    reset (por='00011xxx' mclr='000qquuu')
    bit (names='IRP RP nTO nPD Z DC C' width='1 2 1 1 1 1 1')
sfr (key=FSR addr=0x4 size=1 access='rw rw rw rw rw rw rw rw')
    reset (por='xxxxxxxx' mclr='uuuuuuuu')
    bit (names='FSR' width='8')
    stimulus (scl=rwb pcfiles=rw regfiles=w type=int)
sfr (key=GPIO addr=0x5 size=1 access='u u rw rw r rw rw rw')
    reset (por='--xxxxxx' mclr='--uuuuuu')
    bit (names='- - GP5 GP4 GP3 GP2 GP1 GP0' width='1 1 1 1 1 1 1 1')
    bit (tag=scl names='GP' width='8')
    stimulus (scl=rwb pcfiles=rw regfiles=rw)
UnusedRegs (0x6-0x9)
sfr (key=PCLATH addr=0xa size=1 access='u u u rw rw rw rw rw')
    reset (por='---00000' mclr='---00000')
    bit (names='- - - PCLATH' width='1 1 1 5')
    stimulus (scl=rwb pcfiles=rw regfiles=w type=int)
sfr (key=INTCON addr=0xb size=1 access='rw rw rw rw rw rw rw rw')
    reset (por='00000000' mclr='0000000u')
    bit (names='GIE PEIE T0IE INTE RAIE T0IF INTF RAIF' width='1 1 1 1 1 1 1 1')
    stimulus (scl=rwb pcfiles=rw regfiles=w)
sfr (key=PIR1 addr=0xc size=1 access='rw rw r u rw rw u rw')
    reset (por='000-00-0' mclr='000-00-0')
    bit (names='EEIF LVDIF CRIF - C1IF OSFIF - TMR1IF' width='1 1 1 1 1 1 1 1')
    stimulus (scl=rwb pcfiles=rw regfiles=w)
UnusedRegs (0xd-0xd)
sfr (key=TMR1 addr=0xe size=2 flags=j)
    bit (names='TMR1' width='16')
    stimulus (scl=rwb regfiles=w type=int)
sfr (key=TMR1L addr=0xe size=1 access='rw rw rw rw rw rw rw rw')
    reset (por='xxxxxxxx' mclr='uuuuuuuu')
    bit (names='TMR1L' width='8')
    stimulus (scl=rwb pcfiles=w regfiles=w type=int)
sfr (key=TMR1H addr=0xf size=1 access='rw rw rw rw rw rw rw rw')
    reset (por='xxxxxxxx' mclr='uuuuuuuu')
    bit (names='TMR1H' width='8')
    stimulus (scl=rwb pcfiles=w regfiles=w type=int)
sfr (key=T1CON addr=0x10 size=1 access='rw rw rw rw rw rw rw rw')
    reset (por='00000000' mclr='uuuuuuuu')
    bit (names='T1GINV TMR1GE T1CKPS T1OSCEN nT1SYNC TMR1CS TMR1ON' width='1 1 2 1 1 1 1')
    stimulus (scl=rwb regfiles=w)
UnusedRegs (0x11-0x17)
sfr (key=WDTCON addr=0x18 size=1 access='u u u rw rw rw rw rw')
    reset (por='---01000' mclr='---01000')
    bit (names='- - - WDTPS SWDTEN' width='1 1 1 4 1')
    stimulus (scl=rwb pcfiles=rw regfiles=w)
sfr (key=CMCON0 addr=0x19 size=1 access='u r u rw rw rw rw rw')
    reset (por='-0-00000' mclr='-0-00000')
    bit (names='- COUT - CINV CIS CM' width='1 1 1 1 1 3')
    stimulus (scl=rwb regfiles=w)
sfr (key=CMCON1 addr=0x1a size=1 access='u u u u u u rw rw')
    reset (por='------10' mclr='------10')
    bit (names='- - - - - - T1GSS CMSYNC' width='1 1 1 1 1 1 1 1')
    stimulus (scl=rwb regfiles=w)
UnusedRegs (0x1b-0x1f)
sfr (key=OPTION_REG addr=0x81 size=1 access='rw rw rw rw rw rw rw rw')
    reset (por='11111111' mclr='11111111')
    bit (names='nRAPU INTEDG T0CS T0SE PSA PS' width='1 1 1 1 1 3')
    stimulus (scl=rwb regfiles=w)
sfr (key=TRISIO addr=0x85 size=1 access='u u rw rw r rw rw rw')
    reset (por='--111111' mclr='--111111')
    bit (names='- - TRISIO5 TRISIO4 TRISIO3 TRISIO2 TRISIO1 TRISIO0' width='1 1 1 1 1 1 1 1')
    bit (tag=scl names='TRISIO' width='8')
    stimulus (scl=rwb regfiles=w)
UnusedRegs (0x86-0x89)
sfr (key=PIE1 addr=0x8c size=1 access='rw rw rw u rw rw u rw')
    reset (por='000-00-0' mclr='000-00-0')
    bit (names='EEIE LVDIE CRIE - C1IE OSFIE - TMR1IE' width='1 1 1 1 1 1 1 1')
    stimulus (scl=rwb pcfiles=rw regfiles=w)
UnusedRegs (0x8d-0x8d)
sfr (key=PCON addr=0x8e size=1 access='u u rw rw rw u rw rw')
    reset (por='--010-qq' mclr='--0u0-uu')
    bit (names='- - ULPWUE SBOREN nWUR - nPOR nBOR' width='1 1 1 1 1 1 1 1')
    stimulus (scl=rwb regfiles=w)
sfr (key=OSCCON addr=0x8f size=1 access='u rw rw rw r r r rw')
    reset (por='-110x000' mclr='-110x000')
    bit (names='- IRCF OSTS HTS LTS SCS' width='1 3 1 1 1 1')
    stimulus (scl=rwb pcfiles=rw regfiles=w)
sfr (key=OSCTUNE addr=0x90 size=1 access='u u u rw rw rw rw rw')
    reset (por='---00000' mclr='---uuuuu')
    bit (names='- - - TUN' width='1 1 1 5')
    stimulus (scl=rwb pcfiles=rw regfiles=w)
UnusedRegs (0x91-0x93)
sfr (key=LVDCON addr=0x94 size=1 access='u u rw rw u rw rw rw')
    reset (por='--00-000' mclr='--00-000')
    bit (names='- - IRVST LVDEN - LVDL' width='1 1 1 1 1 3')
    stimulus (scl=rwb pcfiles=rw regfiles=w)
sfr (key=WPUDA addr=0x95 size=1 access='u u rw rw u rw rw rw')
    reset (por='--11-111' mclr='--11-111')
    bit (names='- - WPUDA5 WPUDA4 - WPUDA2 WPUDA1 WPUDA0' width='1 1 1 1 1 1 1 1')
    stimulus (scl=rwb regfiles=w)
sfr (key=IOCA addr=0x96 size=1 access='u u rw rw rw rw rw rw')
    reset (por='--000000' mclr='--000000')
    bit (names='- - IOCA5 IOCA4 IOCA3 IOCA2 IOCA1 IOCA0' width='1 1 1 1 1 1 1 1')
    stimulus (scl=rwb regfiles=w)
sfr (key=WDA addr=0x97 size=1 access='u u rw rw u rw rw rw')
    reset (por='--11-111' mclr='--11-111')
    bit (names='- - WDA5 WDA4 - WDA2 WDA1 WDA0' width='1 1 1 1 1 1 1 1')
    stimulus (scl=rwb regfiles=w)
UnusedRegs (0x98-0x98)
sfr (key=VRCON addr=0x99 size=1 access='rw u rw u rw rw rw rw')
    reset (por='0-0-0000' mclr='0-0-0000')
    bit (names='VREN - VRR - VR' width='1 1 1 1 4')
    stimulus (scl=rwb regfiles=w)
sfr (key=EEDAT addr=0x9a size=1 access='rw rw rw rw rw rw rw rw')
    reset (por='00000000' mclr='00000000')
    bit (names='EEDAT' width='8')
    stimulus (scl=rwb pcfiles=rw regfiles=rw)
sfr (key=EEADR addr=0x9b size=1 access='rw rw rw rw rw rw rw rw')
    reset (por='00000000' mclr='00000000')
    bit (names='EEADR' width='8')
    stimulus (scl=rwb pcfiles=rw regfiles=w)
sfr (key=EECON1 addr=0x9c size=1 access='u u u u rw rw rs rs')
    reset (por='----x000' mclr='----q000')
    bit (names='- - - - WRERR WREN WR RD' width='1 1 1 1 1 1 1 1')
    stimulus (scl=rwb pcfiles=rw regfiles=w)
sfr (key=EECON2 addr=0x9d size=1 access='w w w w w w w w')
    reset (por='--------' mclr='--------')
    bit (names='EECON2' width='8')
UnusedRegs (0x9e-0x9f)
UnusedRegs (0x106-0x109)
UnusedRegs (0x10c-0x10f)
sfr (key=CRCON addr=0x110 size=1 access='rs rw u u u u rw rw')
    reset (por='00----00' mclr='00----00')
    bit (names='GO/nDONE ENC/nDEC - - - - CRREG' width='1 1 1 1 1 1 2')
    bit (tag=scl names='GO_nDONE ENC_nDEC - - - - CRREG' width='1 1 1 1 1 1 2')
    stimulus (scl=rwb regfiles=w)
sfr (key=CRDAT0 addr=0x111 size=1 access='rw rw rw rw rw rw rw rw')
    reset (por='00000000' mclr='00000000')
    bit (names='CRDAT0' width='8')
    stimulus (scl=rwb regfiles=w)
sfr (key=CRDAT1 addr=0x112 size=1 access='rw rw rw rw rw rw rw rw')
    reset (por='00000000' mclr='00000000')
    bit (names='CRDAT1' width='8')
    stimulus (scl=rwb regfiles=w)
sfr (key=CRDAT2 addr=0x113 size=1 access='rw rw rw rw rw rw rw rw')
    reset (por='00000000' mclr='00000000')
    bit (names='CRDAT2' width='8')
    stimulus (scl=rwb regfiles=w)
sfr (key=CRDAT3 addr=0x114 size=1 access='rw rw rw rw rw rw rw rw')
    reset (por='00000000' mclr='00000000')
    bit (names='CRDAT3' width='8')
    stimulus (scl=rwb regfiles=w)
UnusedRegs (0x115-0x11f)
UnusedRegs (0x186-0x189)
UnusedRegs (0x18c-0x19f)

######################################################################
#
# Non Memory-Mapped Registers
#
# (Conditionally visible SFRs appear as NMMRs in the "Special Function
# Registers" section.)
#
######################################################################

HasNMMR=1
nmmr (key=WREG addr=0x0 size=1 access='rw rw rw rw rw rw rw rw')
    reset (por='00000000' mclr='00000000')
nmmr (key=STKPTR addr=0x1 size=1 flags=h access='rw rw rw rw rw rw rw')
    reset (por='00000000' mclr='00000000')
NMMRObjSize=2

######################################################################
#
# Configuration Registers
#
######################################################################

cfgbits (key=CONFIG addr=0x2007 unused=0xe000)
    field (key=OSC mask=0x7 desc="Oscillator Selection bits")
        setting (req=0x7 value=0x7 desc="RC oscillator: CLKOUT function on RA4/T1G/OSC2/CLKOUT pin, RC on RA5/T1CKI/OSC1/CLKIN")
        setting (req=0x7 value=0x6 desc="RCIO oscillator: I/O function on RA4/T1G/OSC2/CLKOUT pin, RC on RA5/T1CKI/OSC1/CLKIN")
        setting (req=0x7 value=0x5 desc="INTOSC oscillator: CLKOUT function on RA4/T1G/OSC2/CLKOUT pin, I/O function on RA5/T1CKI/OSC1/CLKIN")
        setting (req=0x7 value=0x4 desc="INTOSCIO oscillator: I/O function on RA4/T1G/OSC2/CLKOUT pin, I/O function on RA5/T1CKI/OSC1/CLKIN")
        setting (req=0x7 value=0x3 desc="EC: I/O function on RA4/T1G/OSC2/CLKOUT, CLKIN on RA5/T1CKI/OSC1/CLKIN")
        setting (req=0x7 value=0x2 desc="HS oscillator: High-speed crystal/resonator on RA5/T1CKI/OSC1/CLKIN and RA4/T1G/OSC2/CLKOUT")
        setting (req=0x7 value=0x1 desc="XT oscillator: Crystal/resonator on RA5/T1CKI/OSC1/CLKIN and RA4/T1G/OSC2/CLKOUT")
        setting (req=0x7 value=0x0 desc="LP oscillator: Low-power crystal on RA5/T1CKI/OSC1/CLKIN and RA4/T1G/OSC2/CLKOUT")
    field (key=WDTE mask=0x8 desc="Watchdog Timer Enable bit" min=1)
        setting (req=0x8 value=0x8 desc="Enabled")
        setting (req=0x8 value=0x0 desc="Disabled")
    field (key=PUT mask=0x10 desc="Power-up Timer Enable bit")
        setting (req=0x10 value=0x10 desc="Disabled")
        setting (req=0x10 value=0x0 desc="Enabled")
    field (key=MCLRE mask=0x20 desc="MCLR pin function select bit")
        setting (req=0x20 value=0x20 desc="Enabled")
        setting (req=0x20 value=0x0 desc="Disabled")
    field (key=CP mask=0x40 desc="Code Protection bit")
        setting (req=0x40 value=0x40 desc="Disabled")
            checksum (type=0x0 protregion=0x0-0x0)
        setting (req=0x40 value=0x0 desc="Enabled")
            checksum (type=0x20 protregion=0x0-0x3ff)
    field (key=CPD mask=0x80 desc="Data Code Protection bit")
        setting (req=0x80 value=0x80 desc="Disabled")
        setting (req=0x80 value=0x0 desc="Enabled")
    field (key=BOD mask=0x300 desc="Brown-out Reset Selection bits")
        setting (req=0x300 value=0x300 desc="Enabled")
        setting (req=0x300 value=0x200 desc="BOD enabled while running and disabled in Sleep. SBODEN bit disabled.")
        setting (req=0x300 value=0x100 desc="SBODEN controls BOD function")
        setting (req=0x300 value=0x0 desc="Disabled")
    field (key=IESO mask=0x400 desc="Internal-External Switchover bit")
        setting (req=0x400 value=0x400 desc="Enabled")
        setting (req=0x400 value=0x0 desc="Disabled")
    field (key=FCMEN mask=0x800 desc="Fail-Safe Clock Monitor Enable bit")
        setting (req=0x800 value=0x800 desc="Enabled")
        setting (req=0x800 value=0x0 desc="Disabled")
    field (key=WURE mask=0x1000 desc="Wake-Up Reset Enable bit")
        setting (req=0x1000 value=0x1000 desc="Disabled")
        setting (req=0x1000 value=0x0 desc="Enabled")
